Preliminary Technical Data

AD7933/AD7934

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

W/B

DB0

DB1

DB4

DB3

DB2

CS

AGND

DB5

DB6

DB7

DB9

DGND

RD

WR

CONVST

DB10

DB8/HBEN

DB11

BUSY

CLKIN

AD7933/

AD7934

TOP VIEW

(Not to Scale)

Figure 2. Pin Configuration

Table 5. Pin Function Description

Pin No.

Mnemonic

Description

1

decoupled to AGND with a 0.1 µF capacitor and a 10 µF tantalum capacitor.

2

W/B

Word/Byte Input. When this input is logic high, word transfer mode is enabled and data is transferred to and

from the AD7933/AD7934 in 12-/10-bit words on Pins DB0/DB2 to DB11. When this pin is logic low, byte

transfer mode is enabled. Data and the channel ID is transferred on Pins DB0 to DB7 and Pin DB8/HBEN

assumes its HBEN functionality.

3 to 10

DB0 to DB7

Data Bits 0 to 7. Three-state parallel digital I/O pins that provide the conversion result and also allow the

control register to be programmed. These pins are controlled by CS, RD, and WR. The logic high/low voltage

DB1) are always 0 and the LSB of the conversion result is available on DB2.

11

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the parallel interface of

the AD7933/AD7934 will operate. This pin should be decoupled to DGND. The voltage at this pin may be

12

DGND

Digital Ground. This is the ground reference point for all digital circuitry on the AD7933/AD7934. The DGND

and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a

transient basis.

13

DB8/HBEN

Data Bit 8/High Byte Enable. When W/B is high, this pin acts as Data Bit 8, a three-state I/O pin that is controlled

by CS, RD, and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low, the low byte

of data written to or read from the AD7933/AD7934 is on DB0 to DB7. When HBEN is high, the top four bits of

the data being written to or read from the AD7933/AD7934 are on DB0 to DB3 When reading from the device,

DB4 of the high byte is always 0 and DB5 and DB6 will contain the ID of the channel for which the conversion

result corresponds (see Channel Address Bits in Table 9). When writing to the device, DB4 to DB7 of the high

byte must be all 0s. Note that when reading from the AD7933, the two LSBs in the low byte are 0s and the

remaining 6 bits, conversion data.

14 to 16

DB9 to DB11

Data Bits 9 to 11. Three-state parallel digital I/O pins that provide the conversion result and also allow the

control register to be programmed in word mode. These pins are controlled by CS, RD, and WR. The logic

17

BUSY

Busy Output. Logic output indicating the status of the conversion. The BUSY output goes high following the

falling edge of CONVST and stays high for the duration of the conversion. Once the conversion is complete and

the result is available in the output register, the BUSY output will go low. The track-and-hold returns to track

mode just prior to the falling edge of BUSY, and the acquisition time for the part begins when BUSY goes low.

18

CLKIN

Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the

AD7933/AD7934 takes 13.5 clock cycles. The frequency of the master clock input therefore determines the

conversion time and achievable throughput rate.

19

CONVST

Conversion Start Input. A falling edge on CONVST is used to initiate a conversion. The track-and-hold goes from

track to hold mode on the falling edge of CONVST and the conversion process is initiated at this point.

Following power-down, when operating in the auto shutdown or auto standby mode, a rising edge on

CONVST is used to power up the device.

Rev. PrG | Page 9 of 32