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TC59LM806CFT-60 데이터시트(PDF) 1 Page - Toshiba Semiconductor

부품명 TC59LM806CFT-60
상세설명  4,194,304 / 8,388,608-WORDS x 4 BANKS x 16 / 8-BITS Network FCRAM
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제조업체  TOSHIBA [Toshiba Semiconductor]
홈페이지  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TC59LM806CFT-60 데이터시트(HTML) 1 Page - Toshiba Semiconductor

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TC59LM814/06CFT-50,-55,-60
2002-08-19
1/38
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
4,194,304-WORDS
× 4 BANKS × 16-BITS Network FCRAM
TM
8,388,608-WORDS
× 4 BANKS × 8-BITS Network FCRAM
TM
DESCRIPTION
Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM814/06CFT are Network
FCRAMTM containing 268,435,456 memory cells. TC59LM814CFT is organized as 4,194,304-words × 4 banks s× 16
bits, TC59LM806CFT is organized as 8,388,608 words × 4 banks × 8 bits. TC59LM814/06CFT feature a fully
synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which
enables high performance and simple user interface coexistence. TC59LM814/06CFT can operate fast core cycle
using the FCRAMTM core architecture compared with regular DDR SDRAM.
TC59LM814/06CFT is suitable for Network, Server and other applications where large memory density and low
power consumption are required. The Output Driver for Network FCRAMTM is capable of high quality fast data
transfer under light loading condition.
FEATURES
TC59LM814/06
PARAMETER
-50
-55
-60
CL
= 3
5.5 ns
6 ns
6.5 ns
tCK
Clock Cycle Time (min)
CL
= 4
5 ns
5.5 ns
6 ns
tRC
Random Read/Write Cycle Time (min)
25 ns
27.5 ns
30 ns
tRAC Random Access Time (max)
22 ns
24 ns
26 ns
IDD1S Operating Current (single bank) (max)
190 mA
180 mA
170 mA
lDD2P Power Down Current (max)
2 mA
2 mA
2 mA
lDD6
Self-Refresh Current (max)
3 mA
3 mA
3 mA
Fully Synchronous Operation
• Double Data Rate (DDR)
Data input/output are synchronized with both edges of DQS.
• Differential Clock (CLK and CLK ) inputs
CS , FN and all address input signals are sampled on the positive edge of CLK.
Output data (DQs and DQS) is aligned to the crossings of CLK and CLK .
Fast clock cycle time of 5 ns minimum
Clock: 200 MHz maximum
Data:
400 Mbps/pin maximum
• Quad Independent Banks operation
• Fast cycle and Short Latency
• Bidirectional Data Strobe Signal
• Distributed Auto-Refresh cycle in 7.8 µs
• Self-Refresh
• Power Down Mode
• Variable Write Length Control
• Write Latency = CAS Latency-1
• Programable CAS Latency and Burst Length
CAS Latency = 3, 4
Burst Length = 2, 4
• Organization
TC59LM814CFT: 4,194,304 words × 4 banks × 16 bits
TC59LM806CFT: 8,388,608 words × 4 banks × 8 bits
Power Supply Voltage VDD:
2.5 V ± 0.15 V
VDDQ: 2.5 V ± 0.15 V
• 2.5 V CMOS I/O comply with SSTL-2 (half strength driver)
• Package:
400 × 875 mil, 66 pin TSOPII, 0.65 mm pin pitch (TSOPII66-P-400-0.65)
Notice: FCRAM is a trademark of Fujitsu Limited, Japan.


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