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LM2745MTC 데이터시트(PDF) 4 Page - National Semiconductor (TI) |
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LM2745MTC 데이터시트(HTML) 4 Page - National Semiconductor (TI) |
4 / 23 page Electrical Characteristics (Continued) V CC = 3.3V unless otherwise indicated. Typicals and limits appearing in plain type apply for TA=TJ= 25˚C. Limits appearing in boldface type apply over full Operating Temperature Range. Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Symbol Parameter Conditions Min Typ Max Units GATE DRIVE I Q-BOOT BOOT Pin Quiescent Current V BOOT = 12V, VSD =0 18 90 µA R HG_UP High-Side MOSFET Driver Pull-Up ON resistance V BOOT =5V @ 350 mA Sourcing 2.7 Ω R HG_DN High-Side MOSFET Driver Pull-Down ON resistance 350 mA Sinking 0.8 Ω R LG_UP Low-Side MOSFET Driver Pull-Up ON resistance V BOOT =5V @ 350 mA Sourcing 2.7 Ω R LG_DN Low-Side MOSFET Driver Pull-Down ON resistance 350 mA Sinking 0.8 Ω OSCILLATOR f SW PWM Frequency R FADJ = 750 k Ω 50 kHz R FADJ = 100 k Ω 300 R FADJ = 42.2 k Ω 475 600 725 R FADJ = 18.7 k Ω 1000 LM2745 External Synchronizing Signal Frequency Voltage Swing = 0V to V CC 250 1000 SYNC L LM2745 Synchronization Signal Low Threshold f SW = 250 kHz to 1 MHz 1 V SYNC H LM2745 Synchronization Signal High Threshold f SW = 250 kHz to 1 MHz 2 V D MAX Max High-Side Duty Cycle f SW = 300 kHz f SW = 600 kHz f SW = 1 MHz 86 78 67 % LOGIC INPUTS AND OUTPUTS V STBY-IH Standby High Trip Point V FB = 0.575V, VBOOT = 3.3V V SD Rising 1.1 V V STBY-IL Standby Low Trip Point V FB = 0.575V, VBOOT = 3.3V V SD Falling 0.232 V V SD-IH SD Pin Logic High Trip Point V SD Rising 1.3 V V SD-IL SD Pin Logic Low Trip Point V SD Falling 0.8 V V PWGD-TH-LO PWGD Pin Trip Points V FB Falling 0.408 0.434 0.457 V V PWGD-TH-HI PWGD Pin Trip Points V FB Rising 0.677 0.710 0.742 V V PWGD-HYS PWGD Hysteresis V FB Falling V FB Rising 60 90 mV Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which the device operates correctly. Operating Ratings do not imply guaranteed performance limits. Note 2: The power MOSFETs can run on a separate 1V to 14V rail (Input voltage, VIN). Practical lower limit of VIN depends on selection of the external MOSFET. See the MOSFET GATE DRIVERS section under Application Information for further details. Note 3: ESD using the human body model which is a 100pF capacitor discharged through a 1.5 k Ω resistor into each pin. www.national.com 4 |
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