전자부품 데이터시트 검색엔진 |
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544MI-01 데이터시트(PDF) 2 Page - Integrated Circuit Systems |
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544MI-01 데이터시트(HTML) 2 Page - Integrated Circuit Systems |
2 / 7 page Clock Divider MDS 544M-01 A 2 Revision 041505 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com ICS544-01 PRELIM INAR Y INFO RMA T ION Pin Assignment 8-pin (150 mil) SOIC Clock Divider Table 0 = connect directly to ground 1 = connect directly to VDD Pin Descriptions External Components Series Termination Resistor Clock output traces over one inch should use series termination. To series terminate a 50 Ω trace (a commonly used trace impedance), place a 33 Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20 Ω. On chip capacitors- Crystal capacitors should be connected from pins X1 to ground and X2 to ground to optimize the initial accuracy. The value (in pf) of these crystal caps equal (CL-12)*2 in this equation, CL=crystal load capacitance in pf. For example, for a crystal with a 16 pF load cap, each external crystal cap would be 8 pF. [(16-12)x2]=8. Decoupling Capacitor As with any high-performance mixed-signal IC, the ICS544-01 must be isolated from system power supply noise to perform optimally. A decoupling capacitor of 0.01µF must be connected between VDD and the PCB ground plane. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) The 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the X1/ICLK X2 GND VDD S0 OE CLK S1 1 2 3 4 8 7 6 5 S1 S0 CLK 0 0 Input/32 0 1 Input/64 10 Input/256 11 Input/512 Pin Number Pin Name Pin Type Pin Description 1 X1/ICLK XI Crystal or Clock input. 2 X2 Xo Connect to crystal for crystal input and leave open for clock input. 3 GND Power Connect to ground. 4 S0 Input Select 0 for output clock. Connect to GND or VDD, per divider table above. Internal pull-up resistor. 5 CLK Output Clock output per table above. 6 OE Input Output Enable.Tri-states output clock when low. Also shuts down the oscillator circuit. Internal pull-up resistor. OE=1 normal operation. 7 VDD Power Connect to 2.25 V to 3.6 V. 8 S1 Input Select 1 for output clock. Connect to GND or VDD, per divider table above. Internal pull-up resistor. |
유사한 부품 번호 - 544MI-01 |
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유사한 설명 - 544MI-01 |
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