YSS932

8

FUNCTION DESCRIPTION

YSS932 consists of three blocks; the Main DSP block where AC-3 / Pro Logic II / DTS decoding is executed,

the Sub DSP block where various sound field effects are added and the SPDIF receiver (DIR) block.

The Sub DSP is a 8 channel input / 8 channel output programmable DSP exclusively for sound field

processing. It can apply such effects as simulation surround, output configuration and virtual surround. In

addition, with SRAM or DRAM connected, it can produce reverberation up to 2.73 seconds delay at fs=48kHz.

By using this function, it is possible to simulate various sound fields such as a hall or a church.

The SPDIF receiver (DIR) can handle the digital audio interface format input signals of the sampling

frequency 32kHz through 96kHz.

Note)

If adopting some technology owned by another company is desired for use in Sub DSP block, note that a separate

contract may be required between the owner of that technology and the user with respect to adoption of the

technology.

PIN DESCRIPTION

1) DIR Block

1-1) Digital audio interface signal input

DDIN0-3

Input digital audio interface format signal (DAIF signal) into these pins. Then the signal selected by control

register DDINSEL0, 1 is input to the DIR block.

As the pull-up resistors are not built in, connect the unnecessary pins to VSS.

Also, DDIN1, 2, 3 are served as IPORT5, 6, 7. If they are not used as DDIN input pins, they are usable as

general purpose input ports.

1-2) Clock

DIRMCK

The master clock for such peripheral devices as DAC and ADC is output.

The operation mode of DIRMCK is selected according to the lock condition of PLL in the DIR block and

settings for the control register. The DIRMCK output modes are as follows.

- When PLL in the DIR block is not locked (/LOCK=H) ----- (1)

DIRMCK outputs 12.288MHz.

- When PLL in the DIR block is locked (/LOCK=L) and CKMOD=1 ----- (2)

DIRMCK outputs 12.288MHz

- When PLL in the DIR block is locked (/LOCK=L) and CKMOD=0

DIRMCK outputs according to the setting of LOCKMOD1-0.

LOCKMOD1

LOCKMOD0

Normal rate

Double rate

0

0

256fs

256fs

0

1

256fs

128fs

1

∗

256fs

12.288MHz -(3)

The mode like the above (1), (2) and (3) in which the XI's divided clock of 12.288 MHz is output from

DIRMCK is referred to as "free-run mode".