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GS74116J-10I 데이터시트(PDF) 6 Page - GSI Technology |
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GS74116J-10I 데이터시트(HTML) 6 Page - GSI Technology |
6 / 14 page Rev: 2.02 3/2000 6/14 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. N GS74116TP/J/U AC Characteristics * These parameters are sampled and are not 100% tested Read Cycle 1: CE = OE = VIL, WE = VIH, UB and, or LB = VIL Read Cycle Parameter Symbol -8 -10 -12 -15 Unit Min Max Min Max Min Max Min Max Read cycle time tRC 8 --- 10 --- 12 --- 15 --- ns Address access time tAA --- 8 --- 10 --- 12 --- 15 ns Chip enable access time (CE) tAC --- 8 --- 10 --- 12 --- 15 ns Byte enable access time (UB, LB) tAB --- 3.5 --- 4 --- 5 --- 6 ns Output enable to output valid (OE) tOE --- 3.5 --- 4 --- 5 --- 6 ns Output hold from address change tOH 3 --- 3 --- 3 --- 3 --- ns Chip enable to output in low Z (CE) tLZ* 3 --- 3 --- 3 --- 3 --- ns Output enable to output in low Z (OE) tOLZ* 0 --- 0 --- 0 --- 0 --- ns Byte enable to output in low Z (UB, LB) tBLZ* 0 --- 0 --- 0 --- 0 --- ns Chip disable to output in High Z (CE) tHZ* --- 4 --- 5 --- 6 --- 7 ns Output disable to output in High Z (OE) tOHZ* --- 3.5 --- 4 --- 5 --- 6 ns Byte disable to output in High Z (UB, LB) tBHZ* --- 3.5 --- 4 --- 5 --- 6 ns tAA tOH tRC Address Data Out Previous Data Data valid |
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