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July 2001

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HIGH SPEED:

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LOW POWER DISSIPATION:

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HIGH NOISE IMMUNITY:

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POWER DOWN PROTECTION ON INPUTS

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SYMMETRICAL OUTPUT IMPEDANCE:

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BALANCED PROPAGATION DELAYS:

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OPERATING VOLTAGE RANGE:

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PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 16373

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IMPROVED LATCH-UP IMMUNITY

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DESCRIPTION

The 74VHC16373 is an advanced high-speed

CMOS 16 BIT D-TYPE LATCH with 3 STATE

OUTPUTS NON INVERTING fabricated with

sub-micron silicon gate and double-layer metal

These 16 bit D-TYPE latches are byte controlled

by two latch enable inputs (nLE) and two output

enable inputs(nOE).

While the nLE input is held at a high level, the nQ

outputs will follow the data (D) inputs.

When the nLE is taken LOW, the nQ outputs will

be latched at the logic level of D data inputs.

When the (nOE) input is low, the nQ outputs will

be in a normal logic state (high or low logic level);

when nOE is at high level ,the outputs will be in a

high impedance state.

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage. This device can be

used to interface 5V to 3V.

All inputs and outputs are equipped with protec-

tion circuits against static discharge, giving them

2KV ESD immunity and transient excess voltage.

74VHC16373

16-BIT D-TYPE LATCH

WITH 3-STATE OUTPUTS NON INVERTING

ORDER CODES

PACKAGE

TUBE

T & R

TSSOP

74VHC16373TTR

TSSOP

PIN CONNECTION