IN9270 datasheet(2/11 Pages) INTEGRAL | DTMF RECEIVER High-Performance Silicon-Gate CMOS

2 page

IN9270

PIN DESCRIPTIONS

NAME

DESCRIPTION

ESt

Early steering output. Presents a logic high immediately when the digital

algorithm detects a recognizable tone-pair (signal condition). Any momentary loss

of signal condition will cause ESt to return to a logic low.

Gain Select. Gives access to output of front-end differential amplifier for

connection of feedback resistor.

5,6

Internal Connection. Must be tied to GND.

IN+

Non-Inverting Input

Connections to the front-end

IN-

Inverting Input

differential amplifier.

Clock Input

3.579545 MHz crystal connected between

Clock Output

these pins completes internal oscillator.

Q1-Q4

11-14

3-state data outputs. When enabled by OE, provide the code corresponding to the

last valid tone-pair received.

StD

Delayed steering output. Presents a logic high when a received tone-pair has been

registered and the output latch updated; returns to logic low when the voltage on

St/GT falls below VTSt.

St/GT

Steering input/guard time output (bi-directional). A voltage greater than VTSt,

detected at St causes the device to register the detected tone-pair and update the

output latch. A voltage less than VTSt frees the device to accept a new tone-pair.

The GT output acts to reset the external steering time-constant; its state is a

function of ESt and the voltage on St.

3-state output enable (input). Logic high enables the outputs Q1-Q4. Internal pull-

up.

VCC

Positive power supply, +5 V.

VREF

Reference voltage output, nominally VCC /2. May be used to bias the inputs at

mid-rail.

GND

Negative power supply, normally connected to 0 V.

FUNCTIONAL DESCRIPTION

The IN9270 monolithic DTMF receivers offer small

size, low power consumption and high performance.

The architecture consists of a bandsplit filter section,

which separates the high and low tones of a receiver

pair, followed by a digital counting section which

verifies the frequency and duration of the received

tones before passing the corresponding code to the

output bus.

Filter Section

Separation of the low-group and high-group tones is

achieved byapplying the dual-tone signal to the inputs

of two filters - a sixth order for the high group and an

eight order for the low group. The band-widths of

which correspond to the bands enclosing the low-

group and high-group tones (see Figure 1). The filter

section also incorporates notches at 350 Hz and

440 Hz for exceptional dial-tone rejection. Each filter

output is followed by a second order switched-

capacitor section which smooths the signals prior to

limiting.

Limiting

performed

high-gain

comparators which are provided with hysteresis to

prevent detection of unwanted low-level signals and

noise; the outputs of the comparators provide full-rail

logic swings at the frequencies of the incoming tones.

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