Data Sheet

2 Mbit / 4 Mbit SPI Serial Flash

SST25VF020 / SST25VF040

3

©2004 Silicon Storage Technology, Inc.

S71231-04-000

6/04

PIN DESCRIPTION

TABLE

Symbol

Pin Name

Functions

SCK

Serial Clock

To provide the timing of the serial interface.

Commands, addresses, or input data are latched on the rising edge of the clock input, while output

data is shifted out on the falling edge of the clock input.

SI

Serial Data

Input

To transfer commands, addresses, or data serially into the device.

Inputs are latched on the rising edge of the serial clock.

SO

Serial Data

Output

To transfer data serially out of the device.

Data is shifted out on the falling edge of the serial clock.

CE#

Chip Enable

The device is enabled by a high to low transition on CE#. CE# must remain low for the duration of

any command sequence.

WP#

Write Protect

The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.

HOLD#

Hold

To temporarily stop serial communication with SPI flash memory without resetting the device.

Power Supply

To provide power supply (2.7-3.6V).

Ground

T1.0 1231

1

2

3

4

8

7

6

5

CE#

SO

WP#

VSS

Top View

VDD

HOLD#

SCK

SI

1231 08-wson P2.0

1

2

3

4

8

7

6

5

CE#

SO

WP#

VSS

VDD

HOLD#

SCK

SI

Top View

1231 08-soic P1.0