REV. 0

AD10465

–9–

CURRENT MIRROR

DR OUT

CURRENT MIRROR

Figure 4. Digital Output Stage

CURRENT MIRROR

D0–D13

CURRENT MIRROR

100

Figure 5. Digital Output Stage

200

100

100

TO AD8037

Figure 2. Analog Input Stage

LOADS

LOADS

10k

10k

ENCODE

10k

10k

ENCODE

Figure 3. ENCODE Inputs

THEORY OF OPERATION

The AD10465 is a high dynamic range 14-bit, 65 MHz pipeline

delay (three pipelines) analog-to-digital converter. The custom

analog input section maintains the same input ranges (1 V p-p,

2 V p-p, and 4 V p-p) and input impedance (100

Ω, 200 Ω, and

400

Ω) as the AD10242.

The AD10465 employs four monolithic ADI components per

channel (AD8037, AD8138, AD8031, and AD6644), along with

multiple passive resistor networks and decoupling capacitors to

fully integrate a complete 14-bit analog-to-digital converter.

The input signal is passed through a precision laser-trimmed

resistor divider allowing the user to externally select operation

with a full-scale signal of

±0.5 V, ±1.0 V or ±2.0 V by choosing

the proper input terminal for the application.

The AD10465 analog input includes an AD8037 amplifier

featuring an innovative architecture that maximizes the dynamic

range capability on the amplifiers inputs and outputs. The AD8037

amplifier provides a high input impedance and gain for driving

the AD8138 in a single-ended to differential amplifier configu-

ration. The AD8138 has a –3 dB bandwidth at 300 MHz and

delivers a differential signal with the lowest harmonic distortion

available in a differential amplifier. The AD8138 differential

outputs help balance the differential inputs to the AD6644,

maximizing the performance of the ADC.

The AD8031 provides the buffer for the internal reference of

the AD6644. The internal reference voltage of the AD6644 is

designed to track the offsets and drifts of the ADC and is used

to ensure matching over an extended temperature range of

operation. The reference voltage is connected to the output

common mode input on the AD8138. The AD6644 reference

voltage sets the output common-mode on the AD8138 at 2.4 V,

which is the midsupply level for the AD6644.

The AD6644 has complementary analog input pins, AIN and

AIN.

Each analog input is centered at 2.4 V and should swing

±0.55 V

around this reference. Since AIN and

AIN are 180 degrees out

of phase, the differential analog input signal is 2.2 V peak-to-peak.

Both analog inputs are buffered prior to the first track-and-hold,

TH1. The high state of the ENCODE pulse places TH1 in hold

mode. The held value of TH1 is applied to the input of a 5-bit

coarse ADC1. The digital output of ADC1 drives 14 bits of

precision which is achieved through laser trimming. The output

of DAC1 is subtracted from the delayed analog signal at the

input of TH3 to generate a first residue signal. TH2 provides an

analog pipeline delay to compensate for the digital delay of ADC1.

The first residue signal is applied to a second conversion stage

consisting of a 5-bit ADC2, 5-bit DAC2, and pipeline TH4.

The second DAC requires 10 bits of precision which is met by

the process with no trim. The input to TH5 is a second residue

signal generated by subtracting the quantized output of DAC2

from the first residue signal held by TH4. TH5 drives a final

6-bit ADC3.

The digital outputs from ADC1, ADC2, and ADC3 are added

together and corrected in the digital error correction logic to

generate the final output data. The result is a 14-bit parallel

digital CMOS-compatible word, coded as two’s complement.

USING THE FLEXIBLE INPUT

The AD10465 has been designed with the user’s ease of opera-

tion in mind. Multiple input configurations have been included

on board to allow the user a choice of input signal levels and

input impedance. While the standard inputs are

±0.5 V, ±1.0 V

and

±2.0 V, the user can select the input impedance of the