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MTV312MN64 데이터시트(PDF) 5 Page - List of Unclassifed Manufacturers

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MYSON
TECHNOLOGY
MTV312M64
(Rev 0.99)
Revision 0.99
- 5 -
2001/07/26
FUNCTIONAL DESCRIPTIONS
1. 8051 CPU Core
The CPU core of MTV312M is compatible with the industry standard 8051, which includes 256 bytes RAM,
Special Function Registers (SFR), two timers, five interrupt sources and a serial interface. The CPU core
fetches its program code from the 64K bytes Flash in MTV312M. It uses Port0 and Port2 to access the
“external special function register” (XFR) and external auxiliary RAM (AUXRAM).
The CPU core can run at double rate when FclkE is set. Once the bit is set, the CPU runs as if a 24MHz
X’tal is applied on MTV312M, but the peripherals (IIC, DDC, H/V processor) still run at the original frequency.
Note: All registers listed in this document reside in 8051’s external RAM area (XFR). For internal RAM
memory map, please refer to 8051 spec.
2. Memory Allocation
2.1 Internal Special Function Registers (SFR)
The SFR is a group of registers that are the same as standard 8051.
2.2 Internal RAM
There are total 256 bytes internal RAM in MTV312M, the same as standard 8052.
2.3 External Special Function Registers (XFR)
The XFR is a group of registers allocated in the 8051 external RAM area F00h - FFFh. These registers are
used for special functions. Programs can use "MOVX" instruction to access these registers.
2.4 Auxiliary RAM (AUXRAM)
There are total 512 bytes auxiliary RAM allocated in the 8051 external RAM area 800h - 9FFh. Programs
can use "MOVX" instruction to access the AUXRAM.
2.5 Dual Port RAM (DDCRAM)
There are 256 bytes Dual Port RAM allocated in the 8051 external RAM area E00h - EFFh. Programs can
use "MOVX" instruction to access the RAM. The external DDC1/2 Host can access the RAM as if a 24LC02
EEPROM is connected onto the interface.
800h
9FFh
E00h
EFFh
DDCRAM
Accessible by
indirect external
RAM addressing
(Using MOVX
instruction)
AUXRAM
Accessible by
indirect external
RAM addressing
(Using MOVX
instruction
00h
7Fh
80h
FFh
Internal RAM
Accessible by
indirect
addressing only
(Using
MOV A,@Ri
instruction)
Internal RAM
Accessible by
direct and indirect
addressing
SFR
Accessible by
direct addressing
F00h
FFFh
XFR
Accessible by
indirect external
RAM addressing
(Using MOVX
instruction)


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