MYSON
TECHNOLOGY
MTV312M64
(Rev 0.99)
Revision 0.99
- 9 -
2001/07/26
PORT5 (r/w) :
Port 4 data input/output value.
PORT6 (r/w) :
Port 5 data input/output value.
PORT4 (w) :
Port 6 data output value.
5. PWM DAC
Each output pulse width of PWM DAC converter is controlled by an 8-bit register in XFR. The frequency of
PWM clock is 47KHz or 94KHz, selected by PWMF. And the total duty cycle step of these DAC outputs is
253 or 256, selected by DIV253. If DIV253=1, writing FDH/FEH/FFH to DAC register generates stable high
output. If DIV253=0, the output pulses low at least once even if the DAC register's content is FFH. Writing
00H to DAC register generates stable low output.
Reg name
addr
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DA0
F20h(r/w)
Pulse width of PWM DAC 0
DA1
F21h(r/w)
Pulse width of PWM DAC 1
DA2
F22h(r/w)
Pulse width of PWM DAC 2
DA3
F23h(r/w)
Pulse width of PWM DAC 3
DA4
F24h(r/w)
Pulse width of PWM DAC 4
DA5
F25h(r/w)
Pulse width of PWM DAC 5
DA6
F26h(r/w)
Pulse width of PWM DAC 6
DA7
F27h(r/w)
Pulse width of PWM DAC 7
DA8
F28h(r/w)
Pulse width of PWM DAC 8
DA9
F29h(r/w)
Pulse width of PWM DAC 9
DA10
F2Ah(r/w)
Pulse width of PWM DAC 10
DA11
F2Bh(r/w)
Pulse width of PWM DAC 11
DA12
F2Ch(r/w)
Pulse width of PWM DAC 12
DA13
F2Dh(r/w)
Pulse width of PWM DAC 13
DA0-13 (r/w) :
The output pulse width control for DA0-13.
* All of PWM DAC converters are centered with value 80h after power on.
6. H/V SYNC Processing
The H/V SYNC processing block performs the functions of composite signal separation/insertion. SYNC
inputs presence check, frequency counting, polarity detection and control, as well as the protection of
VBLANK output while VSYNC speeds up in high DDC communication clock rate.
Based on the digital filter, the present and frequency function block treat any pulse shorter than one OSC
period (83.33ns) as noise, between one and two OSC period (83.33ns to 166.67ns) as unknown region, and
longer than two OSC period (166.67ns) as pulse.
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