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GS1524 데이터시트(PDF) 6 Page - Gennum Corporation |
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GS1524 데이터시트(HTML) 6 Page - Gennum Corporation |
6 / 18 page GS1524 Data Sheet 14976 - 7 June 2005 6 of 18 2. Pin Out 2.1 Pin Connections Figure 2-1: 16 PIN SOIC 2.2 Pin Descriptions CLI V CC V EE SDI SDI V EE AGC+ AGC- CD/MUTE V CC V EE SDO SDO V EE MCLADJ BYPASS GS1524 16PIN SOIC TOP VIEW 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Table 2-1: Pin Descriptions Pin Number Name Type Description 1 CLI ANALOG OUTPUT CABLE LENGTH INDICATOR. An analog voltage proportional to the cable length connected to the Serial digital input. Note: CLI is recommended for data rates up to 360Mb/s only. 4,5 SDI, SDI INPUT Serial digital differential input. 7,8 AGC+, AGC- PASSIVE INPUT External AGC capacitor. Should be set to IµF 9 BYPASS LOGIC INPUT Forces the Equalizing and DC RESTORE stages into bypass mode when HIGH. No equalization occurs in this mode. 10 MCLADJ ANALOG INPUT MAXIMUM CABLE LENGTH ADJUST. Adjusts the approximate maximum amount of cable to be equalized (from 0m to the maximum cable length). The output is muted (latched to the last state) when the maximum cable length is achieved. Note: MCLADJ is recommended for data rates up to 360Mb/s 12, 13 SDO, SDO PECL OUTPUT Equalized serial digital differential output. |
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