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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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GS9020ACTVE3 데이터시트(PDF) 9 Page - Gennum Corporation |
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GS9020ACTVE3 데이터시트(HTML) 9 Page - Gennum Corporation |
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9 / 31 page  19922 - 3 9 of 31 The serial data output circuits are shown in Figure 6. The serial data outputs are designed to drive 50-75 Ω controlled impedance traces and can be easily connected to the GS9028 cable driver as shown in Figure 7 and Figure 18. Note that to output proper PECL signal levels, a resistor must be connected between the two serial data outputs. 1.4 Automatic Standard Detection The device automatically detects the incoming video standard. The detected standard is encoded on the STD[3:0] pins and the HOSTIF read table bits as shown in Table 1 and Table 3. Noise immunity is included to ensure that momentary signal corruption does not affect the automatic standards detection function. This built in noise immunity results in delayed detection time during power up and when switching between standards. Delays range from as little as eight lines when switching between component standards to as much as four frames when switching between PAL and NTSC standards. If this delay is intolerable, the user can manually set the standard through the HOSTIF write table. To set the standard manually, the STD_SEL bit must be set HIGH and the S bit and STD[3:0] pins/HOSTIF bits set accordingly. The default standard upon reset of the chip is NTSC 4:2:2 component (13.5MHz Y sampling). The S bit, used for single link data standards only, is encoded in the TRSID word and indicates if the data is in RGB or YCRCB format as per SMPTE RP174. In automatic standard detection mode, the S bit can be read from the HOSTIF read table. In manual mode, the S bit must be set in the HOSTIF write table. 1.5 Parallel Clock Output The PCLKOUT pin provides the output parallel clock. All synchronous I/O are timed relative to PCLKOUT. The following listing shows which I/O's are synchronous and which are not. Timing for synchronous outputs is shown in Figure 3. Timing for synchronous inputs is shown in Figure 2. PIN LOGIC OPR HOST BIT STD_SEL STD[3:0] STD[3:0] S TABLE 1 STANDARD NAME STD[3:0] NTSC 4:2:2 Component with 13.5MHz Y sampling 0000 NTSC Composite 0001 NTSC 4:2:2 16x9 Widescreen with 18MHz Y sampling 0010 NTSC 4:4:4:4 Single Link with 13.5MHz Y sampling 0011 PAL 4:2:2 Component with 13.5MHz Y sampling 0100 PAL Composite 0101 PAL 4:2:2 16x9 Widescreen with 18MHz Y sampling 0110 PAL 4:4:4:4 Single Link with 13.5MHz Y sampling 0111 PIN LOGIC OPR HOST BIT PCLKOUT SYNCHRONOUS ASYNCHRONOUS FL[4:0] P[7:5] S[1:0] SCL/P4 FIFO_RESET INTERRUPT DOUT[9:0] SDA/P3 F[2:0] A[2:0]/P[2:0] VR/W HA/D ANC_DATA CS BLANK_EN FLAG_MAP F_R/W RESET NO_EDH CRC_MODE STD[3:0] VBLANKS/L TRS_ERROR HOSTIF_MODE FIFOE/S FLYWDIS BYPASS_EDH SDO_MODE ANC_CHKSM CLIP_TRS |
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