FW32206T100 datasheet(4/86 Pages) AGERE

부품명	FW32206T100

상세설명	1394a PCI PHY/Link Open Host Controller

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제조업체	AGERE [Agere Systems]

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Agere Systems Inc.

FW322 06 T100

Data Sheet, Rev. 1

1394a PCI PHY/Link Open Host Controller

December 2005

Table of Contents (continued)

Figure

Page

Figure 1. FW322 Conceptual Block Diagram ........................................................................................................... 6

Figure 2. PCI Core Block Diagram ........................................................................................................................... 7

Figure 3. OHCI Core Block Diagram ........................................................................................................................ 8

Figure 4. Link Core Block Diagram ......................................................................................................................... 11

Figure 5. The PHY Core Block Diagram ................................................................................................................. 12

Figure 6. Pin Assignments for the FW322 06 T100 ................................................................................................ 15

Figure 7. Crystal Circuitry ....................................................................................................................................... 77

Figure 8. Bus Timing .............................................................................................................................................. 79

Figure 9. Write Cycle Timing .................................................................................................................................. 79

Figure 10. Data Validity .......................................................................................................................................... 79

Figure 11. Start and Stop Definition ....................................................................................................................... 80

Figure 12. Output Acknowledge ............................................................................................................................. 80

Table

Page

Table 1. Pin Descriptions ....................................................................................................................................... 16

Table 2. Bit-Field Access Tag Description ............................................................................................................. 21

Table 3. PCI Configuration Register Map ............................................................................................................. 21

Table 4. PCI Command Register Description ........................................................................................................ 23

Table 5. PCI Status Register ................................................................................................................................. 24

Table 6. Class Code and Revision ID Register Description .................................................................................. 25

Table 7. Latency Timer and Class Cache Line Size Register Description ........................................................... 25

Table 8. Header Type and BIST Register Description .......................................................................................... 26

Table 9. OHCI Base Address Register Description ............................................................................................... 26

Table 10. PCI Subsystem Identification Register Description ............................................................................... 27

Table 11. Interrupt Line and Pin Register Description ........................................................................................... 28

Table 12. MIN_GNT and MAX_LAT Register Description ..................................................................................... 28

Table 13. PCI OHCI Control Register Description ................................................................................................. 29

Table 14. Capability ID and Next Item Pointer Register Description ..................................................................... 29

Table 15. Power Management Capabilities Register Description ......................................................................... 30

Table 16. Power Management Control and Status Register Description .............................................................. 31

Table 17. Power Management Data Register Description .................................................................................... 32

Table 18. OHCI Register Map ............................................................................................................................... 33

Table 19. OHCI Version Register Description ....................................................................................................... 36

Table 20. GUID ROM Register Description ........................................................................................................... 37

Table 21. Asynchronous Transmit Retries Register Description ........................................................................... 37

Table 22. CSR Data Register Description ............................................................................................................. 38

Table 23. CSR Compare Register Description ...................................................................................................... 38

Table 24. CSR Control Register Description ........................................................................................................ 38

Table 25. Configuration ROM Header Register Description ................................................................................. 39

Table 26. Bus Identification Register Description .................................................................................................. 40

Table 27. Bus Options Register Description .......................................................................................................... 40

Table 28. GUID High Register Description ............................................................................................................ 41

Table 29. GUID Low Register Description ............................................................................................................. 41

Table 30. Configuration ROM Mapping Register Description ................................................................................ 42

Table 31. Posted Write Address Low Register Description ................................................................................... 43

Table 32. Posted Write Address High Register Description .................................................................................. 43

Table 33. Vendor ID Register Description ............................................................................................................. 43

Table 34. Host Controller Control Register Description ......................................................................................... 44

Table 35. SelfID Buffer Pointer Register Description ............................................................................................ 46

유사한 부품 번호 - FW32206T100

제조업체	부품명	데이터시트	상세설명
Agere Systems	FW32206	959Kb / 92P	PCI PHY/Link Open Host Controller Interface
Agere Systems	FW322061394	959Kb / 92P	PCI PHY/Link Open Host Controller Interface

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유사한 설명 - FW32206T100

제조업체	부품명	데이터시트	상세설명
Agere Systems	FW32305	1Mb / 152P	1394A PCI PHY/Link Open Host Controller Interface
	FW322	1Mb / 148P	1394A PCI PHY/Link Open Host Controller Interface
	FW323061394	1Mb / 92P	PCI PHY/Link Open Host Controller Interface
	FW322061394	959Kb / 92P	PCI PHY/Link Open Host Controller Interface
VIA Technologies, Inc.	VT6307	449Kb / 54P	PCI 1394a-2000 Integrated Host Controller
Texas Instruments	TSB43AB22A	518Kb / 112P	[Old version datasheet] INTEGRATED 1394A-2000 OHCI PHY/LINK-LAYER CONTROLLER
	TSB43AB21	656Kb / 109P	[Old version datasheet] INTERGRATED 1394A-2000 OHCI PHY LINK-LAYER CONTROLLER
	TSB43AB21A	557Kb / 116P	[Old version datasheet] Integrated 1394a-2000 OHCI PHY/Link-Layer Controller
	TSB43AB22	519Kb / 112P	[Old version datasheet] INTERGRATED 1394a-2000 OHCI PHY/LINK-LAYER CONTROLLER
	TSB43AB22	99Kb / 7P	[Old version datasheet] Integrated 1394a-2000 OHCI PHY/Link-Layer Controller

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FW32206T100 데이터시트(PDF) 4 Page - Agere Systems

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