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GS8160Z36T-133I 데이터시트(PDF) 11 Page - GSI Technology |
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GS8160Z36T-133I 데이터시트(HTML) 11 Page - GSI Technology |
11 / 24 page GS8160Z18/36T-250/225/200/166/150/133 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 2.17 11/2004 11/24 © 1998, GSI Technology Burst Cycles Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode. Burst Order The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables below for details. Note: There is a pull-up device FT pin and a pull-down device on the ZZ pin, so thosethis input pins can be unconnected and the chip will operate in the default states as specified in the above tables. Burst Counter Sequences BPR 1999.05.18 Mode Pin Functions Mode Name Pin Name State Function Burst Order Control LBO L Linear Burst H Interleaved Burst Output Register Control FT L Flow Through H or NC Pipeline Power Down Control ZZ L or NC Active H Standby, IDD = ISB FLXDrive Output Impedance Control ZQ L High Drive (Low Impedance) H or NC Low Drive (High Impedance) Note: The burst counter wraps to initial state on the 5th clock. Note: The burst counter wraps to initial state on the 5th clock. Linear Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 2nd address 01 00 11 10 3rd address 10 11 00 01 4th address 11 10 01 00 |
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