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GS8180DV18D-133 데이터시트(PDF) 5 Page - GSI Technology |
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GS8180DV18D-133 데이터시트(HTML) 5 Page - GSI Technology |
5 / 28 page GS8180DV18D-250/200/167/133/100 Rev: 2.04 4/2005 5/28 © 2002, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Burst of 4 SigmaQuad SRAM DDR Write The status of the Address Input, W, and R pins are sampled at each rising edge of K. W and R high causes chip disable. A low on the Write Enable-bar pin, W, and a high on the Read Enable-bar pin, R, begins a write cycle. W is always ignored if the previous command was a write command. Data is clocked in by the next rising edge of K, the rising edge of K after that, the next rising edge of K, and finally by the next rising edge of K. Burst of 4 Double Data Rate SigmaQuad SRAM Write First Write A NOP Write B Read C NOP Read D NOP A B C D B+3 A A+1 A+2 A+3 B B+1 B+2 B+3 C C+1 C+2 C+3 D K Kbar Address Rbar Wbar BWx bar D C Cbar Q Special Functions Byte Write Control Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low during the data in sample times in a write sequence. Each write enable command and write address loaded into the RAM provides the base address for a 4 beat data transfer. The x18 version of the RAM, for example, may write 72 bits in association with each address loaded. Any 9-bit byte may be masked in any write sequence. |
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