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GS8640Z36T-167I 데이터시트(PDF) 11 Page - GSI Technology

부품명 GS8640Z36T-167I
상세설명  72Mb Pipelined and Flow Through Synchronous NBT SRAM
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제조업체  GSI [GSI Technology]
홈페이지  http://www.gsitechnology.com
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GS8640Z18/36T-300/250/200/167
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 1/2006
11/25
© 2004, GSI Technology
Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
Mode Pin Functions
Mode Name
Pin Name
State
Function
Burst Order Control
LBO
L
Linear Burst
H
Interleaved Burst
Output Register Control
FT
L
Flow Through
H or NC
Pipeline
Power Down Control
ZZ
L or NC
Active
H
Standby, IDD = ISB
Single/Dual Cycle Deselect Control
SCD
L
Dual Cycle Deselect
H or NC
Single Cycle Deselect
FLXDrive Output Impedance Control
ZQ
L
High Drive (Low Impedance)
H or NC
Low Drive (High Impedance)
9th Bit Enable
PE
L
Activate DQPx I/Os (x18/x3672 mode)
H or NC
Deactivate DQPx I/Os (x16/x3272 mode)
Note:
There is a are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so those this input pins can be
unconnected and the chip will operate in the default states as specified in the above tables.


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