Rev: 1.05 10/2001

4/25

© 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88418/36B-200/180/166/150/133

BPR2000.002.14

GS88418/36 BGA Pin Description

Pin Location

Symbol

Type

Description

P4, N4

I

Address field LSBs and Address Counter Preset Inputs

A2, A3, A5, A6, B3, B5, C2, C3, C5,

C6, G4, R2, R6, T3, T5

An

I

Address Inputs

T4

An

I

Address Inputs (x36 Version)

T2, T6

NC

—

No Connect (x36 Version)

T2, T6

An

I

Address Inputs (x18 Version)

K7, L7, N7, P7, K6, L6, M6, N6, P6

H7, G7, E7, D7, H6, G6, F6, E6, D6

H1, G1, E1, D1, H2, G2, F2, E2, D2

K1, L1, N1, P1, K2, L2, M2, N2, P2

I/O

Data Input and Output pins (x36 Version)

L5, G5, G3, L3

I

P7, N6, L6, K7, H6, G7, F6, E7, D6

D1, E2, G2, H1, K2, L1, M2, N1, P2

I/O

Data Input and Output pins (x18 Version)

L5, G3

I

P6, N7, M6, L7, K6, H7, G6, E6, D7,

D2, E1, F2, G1, H2, K1, L2, N2, P1,

G5, L3, T4

NC

—

No Connect (x18 Version)

K4

CK

I

Clock Input Signal; active high

E4

I

Chip Enable; active low

B2

I

Chip Enable; active high

F4

G

I

Output Enable; active low

T7

ZZ

I

Sleep Mode control; active high

R5

FT

I

Flow Through or Pipeline mode; active low

R3

LBO

I

Linear Burst Order mode; active low

L4

SCD

I

Single Cycle Deselect/Dual Cycle Deselect Mode Control

D4

ZQ

I

FLXDrive Output Impedance Control

(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])

B1, C1, R1, T1, L4, B7, C7, U6, R7,

J3,J5, U2, U3, U4, U5

NC

—

No Connect

J2, C4, J4, R4, J6

I

Core power supply

D3, E3, F3, H3, K3, M3, N3, P3, D5,

E5, F5, H5, K5, M5, N5, P5

I

I/O and Core Ground

A1, F1, J1, M1, U1, A7, F7, J7, M7,

U7

I

Output driver power supply