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GS82032AGT-133I 데이터시트(PDF) 5 Page - GSI Technology

부품명 GS82032AGT-133I
상세설명  64K x 32 2Mb Synchronous Burst SRAM
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제조업체  GSI [GSI Technology]
홈페이지  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS82032AGT-133I 데이터시트(HTML) 5 Page - GSI Technology

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GS82032AT-180/166/150/133/100/66/4/5/6
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.12 10/2004
5/22
© 2000, GSI Technology
Note:
There are pull-up devices on LBO and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will
operate in the default states as specified in the above table.
Burst Counter Sequences
Mode Pin Functions
Mode Name
Pin Name
State
Function
Burst Order Control
LBO
L
Linear Burst
H or NC
Interleaved Burst
Output Register Control
FT
L
Flow Through
H or NC
Pipeline
Power Down Control
ZZ
L or NC
Active
H
Standby, IDD = ISB
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Linear Burst Sequence
A[1:0]
A[1:0]
A[1:0]
A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Interleaved Burst Sequence
A[1:0]
A[1:0]
A[1:0]
A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00


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