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GS832472C-250 데이터시트(PDF) 9 Page - GSI Technology |
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GS832472C-250 데이터시트(HTML) 9 Page - GSI Technology |
9 / 46 page Rev: 1.00 10/2001 9/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) GS832418/36 119-Bump BGA Pin Description Pin Location Symbol Type Description P4, N4 A0, A1 I Address field LSBs and Address Counter Preset Inputs R2, C3, B3, C2, A2, A3, A5, A6, T3, T5, R6, C5, B5, C6, B6, B2 An I Address Inputs T4, T6 An Address Input (x36 Version) T2 NC — No Connect (x36 Version) T2, T6, T4 An I Address Input (x18 Version) K7, L7, N7, P7, K6, L6, M6, N6 H7, G7, E7, D7, H6, G6, F6, E6 H1, G1, E1, D1, H2, G2, F2, E2 K1, L1, N1, P1, K2, L2, M2, N2 DQA1–DQA8 DQB1–DQB8 DQC1–DQC8 DQD1–DQD8 I/O Data Input and Output pins. (x36 Version) P6, D6, D2, P2 DQA9, DQB9, DQC9, DQD9 I/O Data Input and Output pins. (x36 Version) L5, G5, G3, L3 BA, BB, BC, BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low (x36 Version) P7, N6, L6, K7, H6, G7, F6, E7, D6 D1, E2, G2, H1, K2, L1, M2, N1, P2 DQA1–DQA9 DQB1–DQB9 I/O Data Input and Output pins (x18 Version) L5, G3 BA, BB I Byte Write Enable for DQA, DQB I/Os; active low (x18 Version) B1, C1, R1, T1, U6, B7, C7, J3, J5, R7 NC — No Connect P6, N7, M6, L7, K6, H7, G6, E6, D7, D2, E1, F2, G1, H2, K1, L2, N2, P1, G5, L3 NC — No Connect (x18 Version) K4 CK I Clock Input Signal; active high M4 BW I Byte Write—Writes all enabled bytes; active low H4 GW I Global Write Enable—Writes all bytes; active low E4 E1 I Chip Enable; active low F4 G I Output Enable; active low G4 ADV I Burst address counter advance enable; active low A4, B4 ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low T7 ZZ I Sleep mode control; active high R5 FT I Flow Through or Pipeline mode; active low R3 LBO I Linear Burst Order mode; active low D4 ZQ I FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) L4 SCD I Single Cycle Deselect/Dual Cyle Deselect Mode Control (x36 version) U2 TMS I Scan Test Mode Select |
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