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OP16AZMDA 데이터시트(PDF) 3 Page - Analog Devices

부품명 OP16AZMDA
상세설명  Precision JFET-Input Operational Amplifiers
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REV. A
–3–
OP15/OP17
Electrical Characteristics
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Input Offset Voltage
VOS
RS = 50
W
0.4
0.9
mV
Average Input Offset Voltage Drift
1
Without External Trim
TCVOS
25
mV/∞C
With External Trim
TCVOS
RP = 100
W
2
mV/∞C
Input Offset Current
2
IOS
TJ = 125
∞C
0.6
4.0
nA
OP17
TA = 125
∞C, device operating
1.0
8.5
nA
Input Bias Current
2
IB
TJ = 125
∞C
±1.2
±5.0
nA
OP17
TA = 125
∞C, device operating
±2.0
±11
nA
Input Voltage Range
IVR
±10.4
V
Common-Mode Rejection Ratio
CMRR
VCM =
±10.4 V
85
97
dB
Power Supply Rejection Ratio
PSRR
VS =
±10 V to ±18 V
15
57
mV/V
Large Signal Voltage Gain
AVO
RL
≥ 2 kW, VO = ± 10 V
35
120
V/mV
Output Voltage Swing
VO
RL
≥ 10 kW±12
±13
V
NOTES
1Sample tested.
2Input bias current is specified for two different conditions. The T
J = 25
∞C specification is with the junction at ambient temperature; the device operating specification
is with the device operating in a warmed-up condition at 25
∞C ambient. The warmed-up bias current value is correlated to the junction temperature value via the
curves of IB versus TJ and IB versus TA. ADI has a bias current compensation circuit which gives improved bias current over the standard JFET input op amps. I B and
IOS are measured at VCM = 0.
(@ VS =
±15 V, –55 C
£ TA £ 125 C, unless otherwise noted.)
OP15E/OP17E
OP15F/OP17F
OP15G/OP17G
Parameter
Symbol
Conditions
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
Input Offset Voltage
VOS
RS = 50
W
0.3
0.75
0.55
1.5
0.7
3.8
mV
Average Input Offset
Voltage Drift1
Without External Trim TCVOS
25
310
430
mV/∞C
With External Trim
TCVOSn
RP = 100
W
23
4
mV/∞C
Input Offset Current
2
IOS
TJ = 70
∞C
0.04
0.30
0.06
0.45
0.08
0.85
nA
OP15
TA = 70
∞C, Device Operating
0.06
0.55
0.08
0.80
0.10
1.2
nA
TJ = 70
∞C
0.04
0.30
0.06
0.45
0.08
0.85
nA
OP17
TA = 70
∞C, Device Operating
0.07
0.70
0.10
1.1
0.15
1.7
nA
Input Bias Current
2
IB
TJ = 70
∞C
±0.10 ±0.40
±0.12 ±0.60
±0.14 ±0.80 nA
OP15
TA = 70
∞C, Device Operating
±0.13 ±0.75
±0.16 ±1.1
±0.19 ±1.5 nA
TJ = 70
∞C
±0.10 ±0.40
±0.12 ±0.60
±0.14 ±0.80 nA
OP17
TA = 70
∞C, Device Operating
±0.15 ±0.90
±0.20 ±1.4
±0.25 ±2.0 nA
Input Voltage Range
IVR
±10.4
±10.4
±10.25
V
Common-Mode
CMRR
VCM =
±10.4 V
85
98
85
96
dB
Rejection Ratio
VCM =
±10.25 V
80
94
dB
Power Supply
PSRR
VS =
±10 V to ±18 V
13
5713
57
mV/V
Rejection Ratio
VS =
±10 V to ±15 V
20
100
mV/V
Large Signal
AVO
RL
≥ 2 kW
65
200
50
180
35
160
V/mV
Voltage Gain
VO =
±10 V
Output Voltage
VO
RL
≥ 10 kW±12
±13
±12
±13
±12
±13
V
Swing
NOTES
1Sample tested.
2Input bias current is specified for two different conditions. The T
J = 25
∞C specification is with the junction at ambient temperature; the device operating specification
is with the device operating in a warmed-up condition at 25
∞C ambient. The warmed-up bias current value is correlated to the junction temperature value via the
curves of IB versus TJ and IB versus TA. ADI has a bias current compensation circuit which gives improved bias current over the standard JFET input op amps. I B and
IOS are measured at VCM = 0.
ELECTRICAL CHARACTERISTICS
(@ VS =
15 V, 0 C
£ TA £ 70 C for E and F grades, –40 C £ TA £ 85 C for G grades
unless otherwise noted)


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