Philips Semiconductors

Product specification

74ALVCH16374

16-bit edge-triggered D-type flip-flop (3-State)

1998 Jun 18

8

output load.

V

output load.

V

VM

VM

1/fMAX

tw

tPHL

tPLH

CP INPUT

Qn OUTPUT

SW00078

GND

Waveform 1. Clock (CP) to output (Qn) propagation delays, the

clock pulse width and the maximum clock pulse frequency

OE INPUT

GND

OUTPUT

LOW-to-OFF

OFF-to-LOW

OUTPUT

HIGH-to-OFF

OFF-to-HIGH

GND

outputs

enabled

outputs

enabled

outputs

disabled

SW00072

Waveform 2. 3-State enable and disable times

VM

SW00079

GND

Dn

INPUT

GND

VM

Qn

OUTPUT

CP

INPUT

NOTE: The shaded areas indicate when the input is permitted to change

for predictable output performance.

Waveform 3. Data set-up and hold times for the Dn input to the

CP input

TEST CIRCUIT

SWITCH POSITION

PULSE

GENERATOR

RT

VI

D.U.T.

VO

CL

VCC

RL = 500 Ω

Test Circuit for switching times

Open

GND

DEFINITIONS

< 2.7V

TEST

Open

2

2.7V

2.7–3.6V

GND

RL = 500 Ω

SV00906

Waveform 4. Load circuitry for switching times