MC13202/203 Technical Data, Rev. 0.0

4

Freescale Semiconductor

•

Supports star, mesh and tree networks

•

Advanced Encryption Standard (AES) 128-bit security

3

Block Diagrams

Figure 1 shows a simplified block diagram of the MC13202/MC13203 which is an IEEE Standard

802.15.4 compatible transceiver that provides the functions required in the physical layer (PHY)

specification. Figure 2 shows the basic system block diagram for the MC13202/MC13203 in an

application. Interface with the transceiver is accomplished through a 4-wire SPI port and interrupt request

line. The media access control (MAC), drivers, and network and application software (as required) reside

on the host processor. The host can vary from a simple 8-bit device up to a sophisticated 32-bit processor

depending on application requirements.

Figure 1. 802.15.4 modem Simplified Block Diagram

Phase Shift Modulator

RST

GPIO1

GPIO2

GPIO3

GPIO4

XTAL2

XTAL1

RFIN_M

(PAO_M)

PAO_P

PAO_M

MOSI

MISO

SPICLK

RXTXEN

CE

ATTN

GPIO5

GPIO6

GPIO7

Receive

Packet RAM

Transmit

Packet RAM 1

Transmit RAM

Arbiter

Receiv e RAM

Arbiter

PA

VCO

Crystal

Oscillator

Sy mbol

Generation

FCS

Generation

Header

Generation

Sequence

Manager

(Control Logic)

VDDLO2

256 MHz

2.45 GHz

LNA

1st IF Mix er

IF = 65 MHz

2nd IF Mix er

IF = 1 MHz PMA

Decimation

Filter

Matched

Filter

Baseband

Mix er

DCD

CCA

Packet

Processor

IRQ

Arbiter

24 Bit Ev ent Timer

IRQ

16 MHz

AGC

Analog

Regulator

VBATT

Digital

Regulator L

Digital

Regulator H

Power-Up

Control

Logic

Cry stal

Regulator

VCO

Regulator

VDDINT

Programmable

Prescaler

CLKO

4 Programmable

Timer Comparators

Synthesizer

VDDD

VDDVCO

VDDA

VDDLO1

Transmit

Packet RAM 2

T / R

RFIN_P

(PAO_P)

CT_Bias