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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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74F112 데이터시트(PDF) 5 Page - NXP Semiconductors |
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74F112 데이터시트(HTML) 5 Page - NXP Semiconductors |
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5 / 10 page  Philips Semiconductors Product specification 74F112 Dual J-K negative edge-triggered flip-flop February 9, 1990 5 AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITION VCC = +5.0V Tamb = +25°C CL = 50pF RL = 500Ω VCC = +5.0V ± 10% Tamb = 0°C to +70°C CL = 50pF RL = 500Ω VCC = +5.0V ± 10% Tamb = –40°C to +85°C CL = 50pF RL = 500Ω UNIT MIN TYP MAX MIN MAX MIN MAX fMAX Maximum clock frequency Waveform 1 85 100 80 80 MHz tPLH tPHL Propagation delay CP to Qn or Qn Waveform 1 2.0 2.0 5.0 5.0 6.5 6.5 2.0 2.0 7.5 7.5 2.0 2.0 7.5 7.5 ns tPLH tPHL Propagation delay SDn, RD to Qn or Qn Waveform 2,3 2.0 2.0 4.5 4.5 6.5 6.5 2.0 2.0 7.5 7.5 1.5 1.5 7.5 7.5 ns AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER TEST CONDITION VCC = +5.0V Tamb = +25°C CL = 50pF RL = 500Ω VCC = +5.0V ± 10% Tamb = 0°C to +70°C CL = 50pF RL = 500Ω VCC = +5.0V ± 10% Tamb = –40°C to +85°C CL = 50pF RL = 500Ω UNIT MIN TYP MAX MIN MAX MIN MAX tS(H) tS((L) Setup time, High or Low Jn, Kn to CP Waveform 1 4.0 3.5 5.0 4.0 5.0 4.0 ns th(H) th(L) Hold time, High or Low Jn, Kn to CP Waveform 1 0.0 0.0 0.0 0.0 0.0 0.0 ns tW(H) tW(L) CP Pulse width High or Low Waveform 1 4.5 4.5 5.0 5.0 5.0 5.0 ns tW(L) SDn, RD Pulse width Low Waveform 2,3 4.5 5.0 5.0 ns tREC Recovery time SDn, RD to CP Waveform 2,3 4.5 5.0 5.0 ns AC WAVEFORMS For all waveforms, VM = 1.5V. VM VM CPn VM VM VM VM VM VM ts(H) th(H) Jn, Kn Qn VM tw(L) fmax ts(L) th(L) VM VM tPLH Qn tw(H) tPHL tPHL tPLH SF00107 The shaded areas indicate when the input is permitted to change for predictable output performance. Waveform 1. Propagation Delay for Data to Output, Data Setup Time and Hold Times, and Clock Pulse Width |
유사한 부품 번호 - 74F112 |
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유사한 설명 - 74F112 |
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