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74F623 데이터시트(PDF) 2 Page - NXP Semiconductors

부품명 74F623
상세설명  Octal bus transceiver, inverting 3tate
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제조업체  PHILIPS [NXP Semiconductors]
홈페이지  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74F623 데이터시트(HTML) 2 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
74F620/74F623
Transceivers
74F620 Octal Bus Transceiver, Inverting (3-State)
74F623 Octal Bus Transceiver, Non-Inverting (3-State)
2
1990 Apr 6
853–0379 96249
FEATURES
High-impedance NPN base inputs for reduced loading
(70
µA in High and Low states)
Ideal for applications which require high output drive and minimal
bus loading
Octal bidirectional bus interface
3-State buffer outputs sink 64mA and source 15mA
74F620, inverting
74F623, non-inverting
DESCRIPTION
The 74F620 is an octal transceiver featuring inverting 3-State
bus-compatible outputs in both send and receive directions. The
outputs are capable of sinking 64mA and sourcing up to 15mA,
providing very good capacitive drive characteristics. The 74F623 is
a non-inverting version of the 74F620.
These octal bus transceivers are designed for asynchronous
two-way communication between data buses. The control function
implementation allows for maximum flexibility in timing.
These devices allow data transmission from the A bus to the B bus
or from the B bus to the A bus depending upon the logic levels at the
Enable inputs (OEBA and OEAB). The Enable inputs can be used to
disable the device so that the buses are effectively isolated.
The dual-enable configuration gives the 74F620 and 74F623 the
capability to store data by the simultaneous enabling of OEBA and
OEAB. Each output reinforces its input in this transceiver
configuration. Thus, when both control inputs are enabled and all
other data sources to the two sets of the bus lines are at high
impedance, both sets of bus lines (16 in all) will remain in their last
states.
TYPE
TYPICAL
PROPAGATION
DELAY
TYPICAL SUPPLY CURRENT
(TOTAL)
74F620
3.5ns
80mA
74F623
4.5ns
105mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
PKG DWG #
20-pin plastic DIP
N74F620N, N74623N
SOT146-1
20-pin plastic SOL
N74F620D, N74623D
SOT163-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F(U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
A0 - A7, B0 - B7
Data inputs
3.5/1.16
70
µA/70µA
OEBA, OEAB
Output Enable inputs
1.0/0.033
20
µA/20µA
A0 - A7
Data outputs
150/40
3mA/24mA
B0 - B7
Data outputs
750/106.7
15mA/64mA
NOTE: One (1.0) FAST unit load is defined as: 20
µA in the High state and 0.6mA in the Low state.
PIN CONFIGURATION – 74F620
20
19
18
17
16
15
14
13
12
10
11
9
8
7
6
5
4
3
2
1
VCC
B1
B2
B3
B4
B5
B6
B7
OEAB
A1
A2
A3
A4
A5
A6
A7
GND
OEBA
A0
B0
SF01124
PIN CONFIGURATION – 74F623
20
19
18
17
16
15
14
13
12
10
11
9
8
7
6
5
4
3
2
1
VCC
B1
B2
B3
B4
B5
B6
B7
OEAB
A1
A2
A3
A4
A5
A6
A7
GND
OEBA
A0
B0
SF01124


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