전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

74HC190 데이터시트(PDF) 2 Page - NXP Semiconductors

부품명 74HC190
상세설명  Presettable synchronous BCD decade up/down counter
Download  13 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  PHILIPS [NXP Semiconductors]
홈페이지  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74HC190 데이터시트(HTML) 2 Page - NXP Semiconductors

  74HC190 Datasheet HTML 1Page - NXP Semiconductors 74HC190 Datasheet HTML 2Page - NXP Semiconductors 74HC190 Datasheet HTML 3Page - NXP Semiconductors 74HC190 Datasheet HTML 4Page - NXP Semiconductors 74HC190 Datasheet HTML 5Page - NXP Semiconductors 74HC190 Datasheet HTML 6Page - NXP Semiconductors 74HC190 Datasheet HTML 7Page - NXP Semiconductors 74HC190 Datasheet HTML 8Page - NXP Semiconductors 74HC190 Datasheet HTML 9Page - NXP Semiconductors Next Button
Zoom Inzoom in Zoom Outzoom out
 2 / 13 page
background image
December 1990
2
Philips Semiconductors
Product specification
Presettable synchronous BCD decade
up/down counter
74HC/HCT190
FEATURES
• Synchronous reversible counting
• Asynchronous parallel load
• Count enable control for synchronous expansion
• Single up/down control input
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT190 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT190 are asynchronously presettable
up/down BCD decade counters. They contain four
master/slave flip-flops with internal gating and steering
logic to provide asynchronous preset and synchronous
count-up and count-down operation.
Asynchronous parallel load capability permits the counter
to be preset to any desired number. Information present on
the parallel data inputs (D0 to D3) is loaded into the counter
and appears on the outputs when the parallel load (PL)
input is LOW. As indicated in the function table, this
operation overrides the counting function.
Counting is inhibited by a HIGH level on the count enable
(CE) input. When CE is LOW internal state changes are
initiated synchronously by the LOW-to-HIGH transition of
the clock input. The up/down (U/D) input signal determines
the direction of counting as indicated in the function table.
The CE input may go LOW when the clock is in either
state, however, the LOW-to-HIGH CE transition must
occur only when the clock is HIGH. Also, the U/D input
should be changed only when either CE or CP is HIGH.
Overflow/underflow indications are provided by two types
of outputs, the terminal count (TC) and ripple clock (RC).
The TC output is normally LOW and goes HIGH when a
circuit reaches zero in the count-down mode or reaches “9”
in the count-up-mode. The TC output will remain HIGH
until a state change occurs, either by counting or
presetting, or until U/D is changed. Do not use the TC
output as a clock signal because it is subject to decoding
spikes. The TC signal is used internally to enable the RC
output. When TC is HIGH and CE is LOW, the RC output
follows the clock pulse (CP). This feature simplifies the
design of multistage counters as shown in Figs 5 and 6.
In Fig.5, each RC output is used as the clock input to the
next higher stage. It is only necessary to inhibit the first
stage to prevent counting in all stages, since a HIGH on
CE inhibits the RC output pulse as indicated in the function
table. The timing skew between state changes in the first
and last stages is represented by the cumulative delay of
the clock as it ripples through the preceding stages. This
can be a disadvantage of this configuration in some
applications.
Fig.6 shows a method of causing state changes to occur
simultaneously in all stages. The RC outputs propagate
the carry/borrow signals in ripple fashion and all clock
inputs are driven in parallel. In this configuration the
duration of the clock LOW state must be long enough to
allow the negative-going edge of the carry/borrow signal to
ripple through to the last stage before the clock goes
HIGH. Since the RC output of any package goes HIGH
shortly after its CP input goes HIGH there is no such
restriction on the HIGH-state duration of the clock.
In Fig.7, the configuration shown avoids ripple delays and
their associated restrictions. Combining the TC signals
from all the preceding stages forms the CE input for a
given stage. An enable must be included in each carry
gate in order to inhibit counting. The TC output of a given
stage it not affected by its own CE signal therefore the
simple inhibit scheme of Figs 5 and 6 does not apply.


유사한 부품 번호 - 74HC190

제조업체부품명데이터시트상세설명
logo
NXP Semiconductors
74HC191 PHILIPS-74HC191 Datasheet
108Kb / 14P
   Presettable synchronous 4-bit binary up/down counter
December 1990
logo
Nexperia B.V. All right...
74HC191 NEXPERIA-74HC191 Datasheet
296Kb / 18P
   Presettable synchronous 4-bit binary up/down counter
Rev. 6 - 8 September 2021
logo
NXP Semiconductors
74HC191D PHILIPS-74HC191D Datasheet
108Kb / 14P
   Presettable synchronous 4-bit binary up/down counter
December 1990
logo
Nexperia B.V. All right...
74HC191D NEXPERIA-74HC191D Datasheet
296Kb / 18P
   Presettable synchronous 4-bit binary up/down counter
Rev. 6 - 8 September 2021
logo
NXP Semiconductors
74HC191DB PHILIPS-74HC191DB Datasheet
108Kb / 14P
   Presettable synchronous 4-bit binary up/down counter
December 1990
More results

유사한 설명 - 74HC190

제조업체부품명데이터시트상세설명
logo
NXP Semiconductors
74HC192 PHILIPS-74HC192 Datasheet
90Kb / 13P
   Presettable synchronous BCD decade up/down counter
December 1990
logo
Integral Corp.
IN74ACT192 INTEGRAL-IN74ACT192 Datasheet
364Kb / 7P
   PRESETTABLE BCD/DECADE UP/DOWN COUNTER
logo
System Logic Semiconduc...
SL74HC192 SLS-SL74HC192 Datasheet
69Kb / 7P
   Presettable BCD/Decade UP/DOWN Counter
logo
Motorola, Inc
MC74F160A MOTOROLA-MC74F160A Datasheet
103Kb / 4P
   SYNCHRONOUS PRESETTABLE BCD DECADE COUNTER
logo
Fairchild Semiconductor
74F162A FAIRCHILD-74F162A Datasheet
70Kb / 7P
   Synchronous Presettable BCD Decade Counter
74F160A FAIRCHILD-74F160A Datasheet
96Kb / 8P
   Synchronous Presettable BCD Decade Counter
logo
Motorola, Inc
MC74AC160 MOTOROLA-MC74AC160 Datasheet
326Kb / 14P
   Synchronous Presettable BCD Decade Counter
SN54LS192 MOTOROLA-SN54LS192 Datasheet
276Kb / 9P
   PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER
logo
NXP Semiconductors
74AC11160 PHILIPS-74AC11160 Datasheet
271Kb / 10P
   SYNCHRONOUS PRESETTABLE SYNCHRONOUS BCD DECADE COUNTER
October 17 1990
logo
ON Semiconductor
SN54-74LS192 ONSEMI-SN54-74LS192 Datasheet
110Kb / 7P
   PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13


데이터시트 다운로드

Go To PDF Page


링크 URL




개인정보취급방침
ALLDATASHEET.CO.KR
ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com