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74LV161 데이터시트(PDF) 9 Page - NXP Semiconductors |
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74LV161 데이터시트(HTML) 9 Page - NXP Semiconductors |
9 / 16 page Philips Semiconductors Product specification 74LV161 Presettable synchronous 4-bit binary counter; asynchronous reset 1997 May 15 9 AC ELECTRICAL CHARACTERISTICS (Continued) CONDITION LIMITS SYMBOL PARAMETER WAVEFORM CONDITION –40 to +85 °C –40 to +125 °C UNIT VCC(V) MIN TYP1 MAX MIN MAX 1.2 –35 th Hold time D PE CEP CET to Figures4–6 2.0 0 –12 0 ns th Dn, PE, CEP, CET to CP Figures 4 – 6 2.7 0 –9 0 ns 3.0 to 3.6 0 –72 0 Maximum clock 2.0 14 40 12 fmax Maximum clock pulse frequency Figures 1, 6 2.7 19 58 16 MHz ulse frequency 3.0 to 3.6 24 70 20 NOTES: 1. Unless otherwise stated, all typical values are measured at Tamb = 25°C 2. Typical values are measured at VCC = 3.3 V. AC WAVEFORMS VM = 1.5 V at VCC ≥ 2.7 V; VM = 0.5 × VCC at VCC < 2.7 V; VOL and VOH are the typical output voltage drop that occur with the output load. Qn, TC tW SV00576 VM CP INPUT OUTPUT VM tPLH tPHL 1/fmax VOL VOH GND VI Figure 1. Clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width and the maximum clock frequency. trem SV00577 VM MR INPUT CP INPUT VI VI GND GND VOL VOH Qn , TC OUTPUT VM VM tPHL tW Figure 2. Master reset (MR) pulse width, the master reset to output (Qn, TC) propagation delays and the master reset to clock (CP) removal times. SV00578 VM CET INPUT TC OUTPUT VM tPHL tPLH GND VI VOL VOH Figure 3. Input (CET) to output (TC) propagation delays. SV00579 VM VM PE INPUT CP INPUT Dn INPUT VM th tsu tsu tsu tsu th th th GND GND GND VI VI VI The shaded areas indicate when the input is permitted to change for predictable output performance. Figure 4. Set-up and hold times for input (Dn) and parallel enable input (PE). |
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