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74LV377 데이터시트(PDF) 7 Page - NXP Semiconductors |
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74LV377 데이터시트(HTML) 7 Page - NXP Semiconductors |
7 / 12 page Philips Semiconductors Product specification 74LV377 Octal D-type flip-flop with data enable; positive edge-trigger 1998 Jun 10 7 AC WAVEFORMS VM = 1.5V at VCC w 2.7V VM = 0.5V * VCC at VCC t 2.7V VOL and VOH are the typical output voltage drop that occur with the output load. SV00707 VM CP INPUT VOL GND VOH VCC Qn OUTPUT VM tPLH tPHL tW 1/fmax Figure 1. Clock (CP) to output (Qn) propagation delays, the clock pulse width and the maximum clock pulse frequency. VM E INPUT CP INPUT Dn INPUT GND GND GND STABLE VCC VCC VCC VM VM tsu tsu tW th th th tsu SV00671 NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. Figure 2. Data set-up and hold times from the data input (Dn) and from the enable input (E) to the clock (CP). TEST CIRCUIT PULSE GENERATOR RT VI D.U.T. VO CL RL = 1k VCC Test Circuit for switching times DEFINITIONS VCC VI < 2.7V VCC TEST tPLH/tPHL RT = Termination resistance should be equal to ZOUT of pulse generators. 50pF SV00901 RL = Load resistor CL = Load capacitance includes jig and probe capacitance 2.7–3.6V 2.7V Figure 3. Load circuitry for switching times |
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