Limits in standard typeface are for T

less otherwise specified: V

Ω; BankA = BankB =

BankC = Fullscale Current; ENA, ENB, ENC, EN5A, EN3B Bits = “1”; C1 = C2 = C

output current(s) and current setting pins (I

Symbol

Parameter

Condition

Min

Typ

Max

Units

f

PWM

Internal Diode Current PWM

Frequency

20

kHz

V

RESET

Reset Voltage Thresholds

2.7V

≤ V

IN

≤ 5.5V

Reset

0

0.45

V

Normal

Operation

1.2

V

IN

I

V

IO

Serial Bus Voltage Level

2.7V

≤ V

IN

≤ 5.5V (Note 13)

1.4

V

IN

V

V

IL

Input Logic Low "0"

2.7V

≤ V

IN

≤ 5.5V, VIO= 3.0V

0

0.3 x

V

IO

V

V

IH

Input Logic High "1"

2.7V

≤ V

IN

≤ 5.5V, VIO= 3.0V

0.7 x

V

IO

V

IO

V

V

OL

Output Logic Low "0"

I

400

mV

I

t

1

SCL (Clock Period)

2.5

µs

t

2

Data In Setup Time to SCL High

100

ns

t

3

Data Out stable After SCL Low

0

ns

t

4

SDIO Low Setup Time to SCL Low

(Start)

100

ns

t

5

SDIO High Hold Time After SCL

High (Stop)

100

ns

20155013

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of

the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the

Electrical Characteristics tables.

Note 2: All voltages are with respect to the potential at the GND pins.

165˚C (typ.).

Note 4: For detailed soldering specifications and information, please refer to National Semiconductor Application Note 1187: Leadless Leadframe Package

(AN-1187).

Note 5: The human body model is a 100pF capacitor discharged through 1.5k

Ω resistor into each pin. (MIL-STD-883 3015.7)

Note 6: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be

Note 7: Junction-to-ambient thermal resistance is highly dependent on application and board layout. In applications where high maximum power dissipation exists,

special care must be paid to thermal dissipation issues in board design. For more information, please refer to National Semiconductor Application Note 1187:

Leadless Leadframe Package (AN-1187).

Note 8: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.

current regulation. See the Maximum Output Current section of the datasheet for more information.

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