74LVC821A datasheet(6/12 Pages) PHILIPS

부품명	74LVC821A

상세설명	10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger 3-State

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제조업체	PHILIPS [NXP Semiconductors]

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Philips Semiconductors

Product specification

74LVC821A

10-bit D-type flip-flop with 5-volt tolerant

inputs/outputs; positive-edge trigger (3-State)

1998 Sep 25

6

DC ELECTRICAL CHARACTERISTICS

Over recommended operating conditions voltages are referenced to GND (ground = 0V)

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

Temp = -40

°C to +85°C

UNIT

MIN

TYP1

MAX

V

HIGH level Input voltage

VCC = 1.2V

VCC

V

VIH

HIGH level Input voltage

VCC = 2.7 to 3.6V

2.0

V

LOW level Input voltage

VCC = 1.2V

GND

V

VIL

LOW level Input voltage

VCC = 2.7 to 3.6V

0.8

V

VCC = 2.7V; VI = VIH or VIL;IO = –12mA

VCC*0.5

VO

HIGH level output voltage

VCC = 3.0V; VI = VIH or VIL;IO = –100µA

VCC*0.2

VCC

V

VOH

HIGH level output voltage

VCC = 3.0V; VI = VIH or VIL; IO = –18mA

VCC*0.6

V

VCC = 3.0V; VI = VIH or VIL; IO = –24mA

VCC*0.8

VCC = 2.7V; VI = VIH or VIL;IO = 12mA

0.40

VOL

LOW level output voltage

VCC = 3.0V; VI = VIH or VIL;IO = 100µA

0.20

V

VCC = 3.0V; VI = VIH or VIL; IO = 24mA

0.55

I

Input leakage current

VCC =3 6V; V = 5 5V or GND

"01

"5

µA

II

Input leakage current

VCC = 3.6V; VI = 5.5V or GND

"0.1

"5

µA

IOZ

3-State output OFF-state current

VCC = 3.6V; VI = VIH or VIL;VO = 5.5V or GND

0.1

"5

µA

Ioff

Power off leakage supply

VCC = 0.0V; VI or VO = 5.5V

0.1

"10

µA

ICC

Quiescent supply current

VCC = 3.6V; VI = VCC or GND; IO = 0

0.1

10

µA

∆ICC

Additional quiescent supply current

per input pin

VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0

5

500

µA

NOTES:

1. All typical values are at VCC = 3.3V and Tamb = 25°C.

2. The specified overdrive current at the data input forces the data input to the opposite logic input state.

AC CHARACTERISTICS

GND = 0V; tr = tf v 2.5ns; CL = 50pF; RL = 500Ω; Tamb = –40°C to +85°C.

LIMITS

SYMBOL

PARAMETER

WAVEFORM

VCC = 3.3V ±0.3V

VCC = 2.7V

UNIT

MIN

TYP1

MAX

MIN

MAX

tPHL

tPLH

Propagation delay

CP to Qn

Figures 1, 4

1.5

5.4

7.3

1.5

8.5

ns

tPZH

tPZL

3-State output enable time

OE to Qn

Figures 2, 4

1.5

5.5

7.6

1.5

8.8

ns

tPHZ

tPLZ

3-State output disable time

OE to Qn

Figures 2, 4

1.5

3.8

6.2

1.5

6.8

ns

tW

Clock pulse width

HIGH or LOW

Figure 1

3.3

1.7

–

3.3

–

ns

tSU

Setup time

Dn to CP

Figure 3

1.9

0.6

–

0.9

–

ns

th

Hold time

Dn to CP

Figure 3

1.5

0

–

1.5

–

ns

fmax

Maximum clock pulse frequency

Figure 1

150

200

–

150

–

MHz

NOTE:

1. Unless otherwise stated, all typical values are at VCC = 3.3V and Tamb = 25°C.

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