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74LVC827ADB 데이터시트(PDF) 6 Page - NXP Semiconductors |
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74LVC827ADB 데이터시트(HTML) 6 Page - NXP Semiconductors |
6 / 12 page Philips Semiconductors Product specification 74LVC827A 10-bit buffer/line driver with 5-volt tolerant inputs/outputs (3-State) 1998 Sep 04 6 DC ELECTRICAL CHARACTERISTICS (Continued) Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40 °C to +85°C UNIT MIN TYP1 MAX I Input leakage current VCC =3 6V; V = 5 5V or GND Not for I/O pins "01 "5 µA II Input leakage current VCC = 3.6V; VI = 5.5V or GND Not for I/O pins "0.1 "5 µA IOZ 3-State output OFF-state current VCC = 3.6V; VI = VIH or VIL;VO = 5.5V or GND 0.1 "5 µA Ioff Power off leakage supply VCC = 0.0V; VI or VO = 5.5V 0.1 "10 µA ICC Quiescent supply current VCC = 3.6V; VI = VCC or GND; IO = 0 0.1 10 µA ∆ICC Additional quiescent supply current per input pin VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0 5 500 µA NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. 2. The specified overdrive current at the data input forces the data input to the opposite logic input state. AC CHARACTERISTICS GND = 0V; tr = tf v 2.5ns; CL = 50pF; RL = 500Ω; Tamb = –40°C to +85°C. LIMITS SYMBOL PARAMETER WAVEFORM VCC = 3.3V ±0.3V VCC = 2.7V VCC = 1.2V UNIT MIN TYP1 MAX MIN MAX TYP tPHL tPLH Propagation delay 1An to 1Yn; 2An to 2Yn Figures 1, 3 1.5 4.0 6.7 1.5 7.1 15 ns tPZH tPZL 3-State output enable time OE1 to 1Yn; OE2 to 2Yn Figures 2, 3 1.5 5.4 8.5 1.5 9.5 25 ns tPHZ tPLZ 3-State output disable time OE1 to 1Yn; OE2 to 2Yn Figures 2, 3 1.5 4.0 6.7 1.5 7.3 11 ns NOTE: 1. Unless otherwise stated, all typical values are at VCC = 3.3V and Tamb = 25°C. AC WAVEFORMS VM = 1.5V at VCC w 2.7V; VM = 0.5 VCC at VCC t 2.7V. VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3V at VCC w 2.7V; VX = VOL + 0.1 VCC at VCC t 2.7V VY = VOH –0.3V at VCC w 2.7V; VY = VOH – 0.1 VCC at VCC t 2.7V V M An INPUT Yn OUTPUT V M t PLH t PHL GND V I V OL V OH SA00431 Figure 1. The input (An) to output (Yn) propagation delays. outputs disabled outputs enabled outputs enabled tPHZ tPZH tPZL tPLZ OUTPUT HIGH–to–OFF OFF–to–HIGH OUTPUT LOW–to–OFF OFF–to–LOW VM VM OEn INPUT VX VOL VOH VY GND GND VCC VI VM SA00430 Figure 2. 3-State enable and disable times. |
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