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MC145503 데이터시트(PDF) 9 Page - Motorola, Inc |
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MC145503 데이터시트(HTML) 9 Page - Motorola, Inc |
9 / 28 page MC145500 •MC145501•MC145502•MC145503•MC145505 MOTOROLA 9 CCI. The data clock input (DC) can be any frequency be- tween 64 kHz and 4.096 MHz. PIN DESCRIPTIONS DIGITAL VLS Logic Level Select input and TTL Digital Ground VLS controls the logic levels and digital ground reference for all digital inputs and the digital output. These devices can operate with logic levels from full supply (VSS to VDD) or with TTL logic levels using VLS as digital ground. For VLS = VDD, all I/O is full supply (VSS to VDD swing) with CMOS switch points. For VSS < VLS < (VDD – 4 V), all inputs and outputs are TTL compatible with VLS being the digital ground. The pins controlled by VLS are inputs MSI, CCI, TDE, TDC, RCE, RDC, RDD, PDI, and output TDD. MSI Master Synchronization Input MSI is used for determining the sample rate of the transmit side and as a time base for selecting the internal prescale divider for the convert clock input (CCI) pin. The MSI pin should be tied to an 8 kHz clock which may be a frame sync or system sync signal. MSI has no relation to transmit or receive data timing, except for determining the internal trans- mit strobe as described under the TDE pin description. MSI should be derived from the transmit timing in asynchronous applications. In many applications MSI can be tied to TDE. (MSI is tied internally to TDE in MC145503/05.) CCI Convert Clock Input CCI is designed to accept five discrete clock frequencies. These are 128 kHz, 1.536 MHz, 1.544 MHz, 2.048 MHz, or 2.56 MHz. The frequency at this input is compared with MSI and prescale divided to produce the internal sequencing clock at 128 kHz (or 16 times the sampling rate). The duty cycle of CCI is dictated by the minimum pulse width except for 128 kHz, which is used directly for internal sequencing and must have a 40 to 60% duty cycle. In asynchronous applications, CCI should be derived from transmit timing. (CCI is tied internally to TDC in MC145500/01/03.) TDC Transmit Data Clock Input TDC can be any frequency from 64 kHz to 4.096 MHz, and is often tied to CCI if the data rate is equal to one of the five discrete frequencies. This clock is the shift clock for the transmit shift register and its rising edges produce succes- sive data bits at TDD. TDE should be derived from this clock. (TDC and RDC are tied together internally in the MC145505 and are called DC.) CCI is internally tied to TDC on the MC145500/ 01/03. Therefore, TDC must satisfy CCI timing requirements also. TDE Transmit Data Enable Input TDE serves three major functions. The first TDE rising edge following an MSI rising edge generates the internal transmit strobe which initiates an A/D conversion. The inter- nal transmit strobe also transfers a new PCM data word into the transmit shift register (sign bit first) ready to be output at TDD. The TDE pin is the high impedance control for the transmit digital data (TDD) output. As long as this pin is high, the TDD output stays low impedance. This pin also enables the output shift register for clocking out the 8–bit serial PCM word. The logical AND of the TDE pin with the TDC pin clocks out a new data bit at TDD. TDE should be held high for eight consecutive TDC cycles to clock out a complete PCM word for byte interleaved applications. The transmit shift register feeds back on itself to allow multiple reads of the transmit data. If the PCM word is clocked out once per frame in a byte interleaved system, the MSI pin function is transparent and may be connected to TDE. The TDE pin may be cycled during a PCM word for bit in- terleaved applications. TDE controls both the high imped- ance state of the TDD output and the internal shift clock. TDE must fall before TDC rises (tsu8) to ensure integrity of the next data bit. There must be at least two TDC falling edges between the last TDE rising edge of one frame and the first TDE rising edge of the next frame. MSI must be available separate from TDE for bit interleaved applications. TDD Transmit Digital Data Output The output levels at this pin are controlled by the VLS pin. For VLS connected to VDD, the output levels are from VSS to VDD. For a voltage of VLS between VDD – 4 V and VSS, the output levels are TTL compatible with VLS being the digi- tal ground supply. The TDD pin is a three–state output controlled by the TDE pin. The timing of this pin is controlled by TDC and TDE. When in TTL mode, this output may be made high–speed CMOS compatible using a pull–up resis- tor. The data format (Mu–Law, A–Law, or sign magnitude) is controlled by the Mu/A pin. RDC Receive Data Clock Input RDC can be any frequency from 64 kHz to 4.096 MHz. This pin is often tied to the TDC pin for applications that can use a common clock for both transmit and receive data trans- fers. The receive shift register is controlled by the receive clock enable (RCE) pin to clock data into the receive digital data (RDD) pin on falling RDC edges. These three signals can be asynchronous with all other digital pins. The RDC in- put is internally tied to the TDC input on the MC145505 and called DC. RCE Receive Clock Enable Input The rising edge of RCE should identify the sign bit of a re- ceive PCM word on RDD. The next falling edge of RDC, after a rising RCE, loads the first bit of the PCM word into the re- ceive register. The next seven falling edges enter the remain- der of the PCM word. On the ninth rising edge, the receive PCM word is transferred to the receive buffer register and the A/D sequence is interrupted to commence the decode pro- cess. In asynchronous applications with an 8 kHz transmit sample rate, the receive sample rate should be between 7.5 and 8.5 kHz. Two receive PCM words may be decoded and analog summed each transmit frame to allow on–chip con- ferencing. The two PCM words should be clocked in as two single PCM words, a minimum of 31.25 µs apart, with a receive data clock of 512 kHz or faster. |
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