TMP275

SBOS363A − JUNE 2006 − REVISED JUNE 2006

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10

TWO-WIRE TIMING DIAGRAMS

SCL

SDA

t

(LOW)

t

R

t

F

t

(HDSTA)

t

(HDSTA)

t

(HDDAT)

t

(BU F )

t

(SUDAT)

t

(HIGH)

t

(SUSTA)

t

(SUSTO)

PS

SP

Figure 4. Two-Wire Timing Diagram

Frame 1 Two−Wire Slave Address Byte

Frame 2 Pointer Register Byte

Frame 4 Data Byte 2

1

Start By

Master

ACK By

TMP275

ACK By

TMP275

ACK By

TMP275

Stop By

Master

19

1

1

D7

D6

D5

D4

D3

D2

D1

D0

9

Frame 3 Data Byte 1

ACK By

TMP275

1

D7

SDA

(Continued)

SCL

(Continued)

D6

D5

D4

D3

D2

D1

D0

9

9

SDA

SCL

0

0

1

A2

A1A0R/W

0

0

0

0

0

0

P1

P0

…

…

Figure 5. Two-Wire Timing Diagram for TMP275 Write Word Format