ADM1178

Preliminary Technical Data

Rev. PrD | Page 8 of 16

GATE AND TIMER FUNCTIONS DURING A

HOTSWAP

During hot insertion of a board onto a live supply rail at VCC,

the abrupt application of supply voltage charges the external

FET drain/gate capacitance, which could cause an unwanted

gate voltage spike. An internal circuit holds GATE low before

the internal circuitry wakes up. This reduces the FET current

surges substantially at insertion. The GATE pin is also held low

during the initial timing cycle, and until the ON pin has been

taken high to start the hotswap operation.

During hotswap operation the GATE pin is first pulled up by a

12 μA current source. If the current through the sense resistor

reaches the overcurrent fault timing threshold, Voctim, then a

pull-up current of 60 µA on the TIMER pin is turned on, and

this pin starts charging up. At a slightly higher voltage in the

sense resistor, the error amplifier servos the GATE pin to

maintain a constant current to the load by controlling the

A normal hotswap will complete when the board supply

capacitors near full charge and the current through the sense

resistor drops, to eventually reach the level of the board load

current. As soon as the current drops below the overcurrent

fault timing threshold, the current into the TIMER pin will

switch from being a 60 μA pull-up to a 100 μA pull-down. The

ADM1178 will then drive the GATE voltage as high as it can to

A hotswap will fail if the load current fails to drop below the

pin has charged up to 1.3 V. In this case the GATE pin is then

pulled down with a 2 mA current sink. The GATE pull-down

will stay on until a hotswap retry starts, which can be forced by

de-asserting then re-asserting the ON pin, or the device will

retry automatically after a cool-down period, on the ADM1178-

1.

The ADM1178 also features a method of protection from

sudden load current surges, such as a low impedance fault,

when the current seen across the sense resistor may go well

beyond the linear current limit. If the fast overcurrent trip

turned on immediately. This pulls the GATE voltage down

quickly to enable the ADM1178 to limit the length of the

current spike that gets through, and also to bring the current

through the sense resistor back into linear regulation as quickly

as possible. This protects the backplane supply from sustained

overcurrent conditions, which may otherwise have caused

problems with the backplane supply level dropping too low.

CALCULATING CURRENT LIMITS AND FAULT

CURRENT LIMIT TIME

The nominal linear current limit is determined by a sense

resistor connected between the VCC and SENSE pins as given

by the equation below:

(1)

The minimum linear fault current is given by Equation 2:

(2)

The maximum linear fault current is given by Equation 3:

(3)

The power rating of the sense resistor should be rated at the

maximum linear fault current level.

The minimum overcurrent fault timing threshold current is

given by

(4)

The maximum fast overcurrent trip threshold current is given

by

The fault current limit time is the time that a device will spend

timing an overcurrent fault, and is given by

(6)

INITIAL TIMING CYCLE

When VCC is first connected to the backplane supply, there is

an internal supply (time-point (1) in Figure 4) in the ADM1178

which needs to charge up. A very short time later (significantly

less than 1 ms) the internal supply will be fully up and, since the

undervoltage lockout voltage has been exceeded at VCC, the

device will come out of reset. During this first short reset period

the GATE pin is held down with a 25 mA pulldown current,

and the TIMER pin is pulled down with a 100 μA current sink.

The ADM1178 then goes through an initial timing cycle. At

point (2) the TIMER pin is pulled high with 5 µA. At time point

portion of the initial cycle ends. The 100 µA current source

then pulls down the TIMER pin until it reaches 0.2 V at time

point (4). The initial cycle delay (time point 2 to time point 4) is

(7)

When the initial timing cycle terminates, the device is ready to

start a hotswap operation (assuming ON pin is asserted). In the

example shown in Figure 4, the ON pin was asserted at the

same time as VCC was applied, so the hotswap operation starts

immediately after time-point (4). At this point the FET gate is