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AD9397KSTZ-150 데이터시트(PDF) 5 Page - Analog Devices |
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AD9397KSTZ-150 데이터시트(HTML) 5 Page - Analog Devices |
5 / 28 page AD9397 Rev. 0 | Page 5 of 28 Test AD9397KSTZ-100 AD9397KSTZ-150 Parameter Level Conditions Min Typ Max Min Typ Max Unit AC SPECIFICATIONS Intrapair (+ to −) Differential Input Skew (TDPS) IV 360 ps Channel to Channel Differential Input Skew (TCCS) IV 6 Clock Period Low-to-High Transition Time for Data and Controls (DLHT) IV Output drive = high; CL = 10 pF 900 ps IV Output drive = low; CL = 5 pF 1300 ps Low-to-High Transition Time for DATACK (DLHT) IV Output drive = high; CL = 10 pF 650 ps IV Output drive = low; CL = 5 pF 1200 ps High-to-Low Transition Time for Data and Controls (DHLT) IV Output drive = high; CL = 10 pF 850 ps IV Output drive = low; CL = 5 pF 1250 ps High-to-Low Transition Time for DATACK (DHLT) IV Output drive = high; CL = 10 pF 800 ps IV Output drive = low; CL = 5 pF 1200 ps Clock to Data Skew5 (TSKEW) IV −0.5 +2.0 −0.5 +2.0 ns Duty Cycle, DATACK5 IV 45 50 55 % DATACK Frequency (FCIP) VI 20 150 MHz 1 The typical pattern contains a gray scale area, output drive = high. Worst-case pattern is alternating black and white pixels. 2 The typical pattern contains a gray scale area, output drive = high. 3 Specified current and power values with a worst-case pattern (on/off). 4 DATACK load = 10 pF, data load = 5 pF. 5 Drive strength = high. |
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