MC145193

5

MOTOROLA WIRELESS SEMICONDUCTOR

SOLUTIONS – RF AND IF DEVICE DATA

AC INTERFACE CHARACTERISTICS

(VDD = VCC = 2.7 to 5.5 V, TA = – 40 to + 85°C, CL = 25 pF, Input tr = tf = 10 ns; VPD = 2.7 to 5.5 V)

Parameter

Figure

No.

Symbol

Guaranteed

Limit

Unit

Serial Data Clock Frequency (Note: Refer to Clock tw below)

1

fclk

dc to 4.0

MHz

Maximum Propagation Delay, CLK to Output A (Selected as Data Out)

1, 5

tPLH, tPHL

100

ns

Maximum Propagation Delay, ENB to Output A (Selected as Port)

2, 5

tPLH, tPHL

150

ns

Maximum Propagation Delay, ENB to Output B

2, 6

tPZL, tPLZ

150

ns

Maximum Output Transition Time, Output A and Output B; tTHLonly, on Output B

1, 5, 6

tTLH, tTHL

50

ns

Maximum Input Capacitance – Din, ENB, CLK

Cin

10

pF

TIMING REQUIREMENTS

(VDD = VCC = 2.7 to 5.5 V, TA = – 40 to + 85°C, Input tr = tf = 10 ns, unless otherwise indicated)

Parameter

Figure

No.

Symbol

Guaranteed

Limit

Unit

Minimum Setup and Hold Times, Din vs CLK

3

tsu, th

50

ns

Minimum Setup, Hold and Recovery Times, ENB vs CLK

4

tsu, th, trec

100

ns

Minimum Pulse Width, ENB

4

tw

[Note]

cycles

Minimum Pulse Width, CLK

1

tw

125

ns

Maximum Input Rise and Fall Times, CLK

1

tr, tf

100

µs

NOTE:

The minimum limit is 3 REFin cycles or 195 fin cycles, whichever is greater.