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74AUP1G175GF 데이터시트(PDF) 2 Page - NXP Semiconductors |
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74AUP1G175GF 데이터시트(HTML) 2 Page - NXP Semiconductors |
2 / 26 page 74AUP1G175_1 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.xx — 27 March 2006 2 of 26 Philips Semiconductors 74AUP1G175 Low-power D-type flip-flop with reset; positive-edge trigger s Multiple package options s Specified from −40 °Cto+85 °C and −40 °C to +125 °C 3. Quick reference data [1] CPD is used to determine the dynamic power dissipation (PD in µW). PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. [2] The condition is VI = GND to VCC. Table 1: Quick reference data GND = 0 V; Tamb =25 °C; tr =tf ≤ 3ns. Symbol Parameter Conditions Min Typ Max Unit tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay CP to Q CL = 5 pF; RL =1MΩ; VCC = 0.8 V - 21.1 - ns CL = 5 pF; RL =1MΩ; VCC = 1.1 V to 1.3 V 2.4 5.9 11.7 ns CL = 5 pF; RL =1MΩ; VCC = 1.4 V to 1.6 V 2.0 4.1 6.8 ns CL = 5 pF; RL =1MΩ; VCC = 1.65 V to 1.95 V 1.6 3.3 5.4 ns CL = 5 pF; RL =1MΩ; VCC = 2.3 V to 2.7 V 1.3 2.5 3.6 ns CL = 5 pF; RL =1MΩ; VCC = 3.0 V to 3.6 V 1.2 2.1 2.9 ns HIGH-to-LOW and LOW-to-HIGH propagation delay MR to Q CL = 5 pF; RL =1MΩ; VCC = 0.8 V - 17.4 - ns CL = 5 pF; RL =1MΩ; VCC = 1.1 V to 1.3 V 2.4 5.2 9.7 ns CL = 5 pF; RL =1MΩ; VCC = 1.4 V to 1.6 V 2.3 3.8 4.9 ns CL = 5 pF; RL =1MΩ; VCC = 1.65 V to 1.95 V 1.8 3.1 4.9 ns CL = 5 pF; RL =1MΩ; VCC = 2.3 V to 2.7 V 1.8 2.6 3.6 ns CL = 5 pF; RL =1MΩ; VCC = 3.0 V to 3.6 V 1.6 2.4 3.1 ns fmax maximum input clock frequency VCC = 3.0 V to 3.6 V; CL = 30 pF 190 300 - MHz CI input capacitance - 1.5 - pF CPD power dissipation capacitance VCC = 1.8 V; f = 1 MHz [1] [2] - 2.0 - pF VCC = 3.3 V; f = 1 MHz [1] [2] - 2.7 - pF |
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