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S29CD032G0MFFA100 데이터시트(PDF) 31 Page - SPANSION |
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31 / 87 page November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 29 Pr el im i n a r y RESET# Control in Linear Mode The RESET# pin immediately halts the linear burst access when taken to VIL. The DQ data bus signal float. Additionally, the Configuration Register contents are reset back to the default condi- tion where the device is placed in asynchronous access mode. OE# Control in Linear Mode The OE# (Output Enable) pin is used to enable the linear burst data on the DQ data bus pin. De- asserting the OE# pin to VIH during a burst operation floats the data bus. However, the device continues to operate internally as if the burst sequence continues until the linear burst is com- plete. The OE# pin does not halt the burst sequence, this is accomplished by either taking CE# to VIH or re-issuing a new ADV# pulse. The DQ bus remains in the float state until OE# is taken to VIL. IND/WAIT# Operation in Linear Mode The IND/WAIT#, or End of Burst Indicator signal (when in linear modes), informs the system that the last address of a burst sequence is on the DQ data bus. For example, if a 2-double-word linear burst access is enabled using a 16-bit DQ bus (WORD# = VIL), the IND/WAIT# signal transitions active on the second access. If the same scenario is used, the IND/WAIT# signal has the same delay and setup timing as the DQ pins. Also, the IND/WAIT# signal is controlled by the OE# sig- nal. If OE# is at VIH, the IND/WAIT# signal floats and is not driven. If OE# is at VIL, the IND/ WAIT# signal is driven at VIH until it transitions to VIL indicating the end of burst sequence. The IND/WAIT# signal timing and duration is (See Configuration Register on page 31 for more infor- mation). The following table lists the valid combinations of the Configuration Register bits that impact the IND/WAIT# timing. Note: Operation is shown for the 32-bit data bus. Figure shown with 3-CLK initial access delay configuration, linear address, 4-doubleword burst, output on rising CLD edge, data hold for 1-CLK, IND/WAIT# asserted on the last transfer before wrap- around. Figure 2. End of Burst Indicator (IND/WAIT#) Timing for Linear 8-Word Burst Operation Table 31. Valid Configuration Register Bit Definition for IND/WAIT# DOC WC CC Definition 0 0 1 IND/WAIT# = VIL for 1-CLK cycle, Active on last transfer, Driven on rising CLD edge 0 1 1 IND/WAIT# = VIL for 1-CLK cycle, Active on second to last transfer, Driven on rising CLK edge CE# CLK ADV# Addresses OE# Data Address 1 Address 2 Invalid D1 D2 D3 D0 Address 1 Latched 3 Clock Delay IND/WAIT# VIL VIH |
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