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MC13001XP 데이터시트(PDF) 6 Page - Motorola, Inc |
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MC13001XP 데이터시트(HTML) 6 Page - Motorola, Inc |
6 / 10 page MC13001X MC13007X 6 MOTOROLA ANALOG IC DEVICE DATA The oscillator itself is a novel design using an on–chip 50 pF silicon nitride capacitor which has a temperature drift of only 70 ppm/ °C and negligible long term drift. This, in conjunction with an external resistor, gives a drift of horizontal frequency of less than 1.0 Hz/ °C – i.e., less than 100 Hz over the full operating temperature range of the chip. The pull–in range of the PLL is about ±750 Hz, so normally this would eliminate the need for any customer adjustment of the frequency. The second significant feature of this design is the use of a virtual ground at the frequency control point which floats at a potential derived from a divider across the power supply and this is the same divider which determines the end–points of the oscillator ramp. The frequency adjustment which is necessary to take up tolerances in the on–chip capacitor is fed in as a current to this virtual ground, and when this adjustment current is derived from an external potentiometer across the same supply there is no frequency variation with supply voltage. Moreover, using the voltage from a potentiometer for the adjustment instead of the simple variable resistor normally used in RC oscillators makes the frequency independent of the value of the potentiometer and hence its temperature coefficient. The frequency control current from the first phase detector is fed into this same virtual ground, and as the sensitivity of the control is about 230 Hz/ µA, a high value resistor can be used (680 kΩ) which can be directly connected to the phase detector filter without significant loading. This oscillator operates with almost constant frequency to below 4.0 V and as the total PLL system consumes less than 4.0 mA at this voltage, this gives an ideal startup characteristic for receivers using deflection–derived power supplies. The flyback gating input is on Pin 15 which is internally clamped to 0.7 V in both directions and requires a negative input current of 0.6 mA to operate the gate circuit. This input can be a raw flyback pulse simply fed via a suitable resistor. Vertical System An output switching signal is taken from the 31.5 kHz oscillator to clock the vertical counter which is used in place of a conventional vertical oscillator circuit. The counter is reset by the vertical sync pulse, but the period during which it is permitted to reset is controlled by the window control. Normally, when the counter is running synchronously, the window is narrow to give some protection against spurious noise pulses in the sync signal. If the counter output is not coincident with sync however, after a short period the window opens to five reset over a much wider count range, leading to a fast picture roll towards lock. At weak signal, i.e., less than 200 µV IF input, the vertical system is forced to narrow mode to give a steadier picture for commonly occurring types of noise. The vertical sync, gated by the counter, then resets a ramp generator on Pin 20 and the 1.5 Vpp ramp is buffered to Pin 22 by the vertical preamplifier. A differential input to the preamp on Pin 21 compares the signal generated across the resistor in series with the deflection coils with the generated ramp and thus controls shape and amplitude of the coil current. The basic block diagram of the countdown system is shown in Figure 9. The 31.5 kHz (2FH) clock from the horizontal oscillator drives a 10–stage counter circuit which is normally reset by the vertical sync pulse via the sync gate, ‘‘OR’’ gate and D flip–flop. This D input is also used to initiate discharge of the ramp capacitor and hence causes picture flyback. 2FH Clock 0 20 Blanking Latch 10 Stage Counter Counter Reset 514–526 ‘‘Narrow’’ 384–544 ‘‘Wide’’ H/4 Delay Coincidence Detector Vertical Sync COINC 8H/2 Delay 2H/2 Delay Window Control Sync Gate/ Ramp Latch D Flip–Flop (Delay) Define Window for Sync To Ramp Pull–Down Clock Blanking Pulse To ‘‘Wide’’ COINC To ‘‘Narrow’’ D Figure 9. Monomax Vertical Countdown |
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