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MC100EP142FA 데이터시트(PDF) 9 Page - ON Semiconductor

부품명 MC100EP142FA
상세설명  3.3 V / 5 V ECL 9-Bit Shift Register
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제조업체  ONSEMI [ON Semiconductor]
홈페이지  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC100EP142FA 데이터시트(HTML) 9 Page - ON Semiconductor

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MC10EP142, MC100EP142
http://onsemi.com
9
Table 11. AC CHARACTERISTICS VCC = 3.0 V to 5.5 V; VEE = 0.0 V or VCC = 0.0 V; VEE = −3.0 V to −5.5 V (Note 26)
Symbol
Characteristic
−40°C
25°C
85°C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
fSHIFT
Maximum Shift Frequency
2.8
GHz
tPLH,
tPHL
Propagation Delay to Output
CLKx
MR
500
500
625
625
750
750
550
550
675
675
800
800
575
575
700
700
825
825
ps
ts
Setup Time
D
SEL
50
100
−50
50
50
100
−50
50
50
100
−50
50
ps
th
Hold Time
D
SEL
100
50
50
−50
100
50
50
−50
100
50
50
−50
ps
tRR
Reset Recovery Time
800
ps
tpw
Minimum Pulse Width
200
ps
tSKEW
Within-Device Skew (Note 27)
Q, Q
Duty Cycle Skew (Note 28)
50
5.0
100
20
50
5.0
100
20
50
5.0
100
20
ps
tJITTER
Random Clock Jitter (Figure 4)
1
2
1
2
1
2
ps
Vinpp
Input Voltage Swing/Sensitivity
(Differential Configuration)
150
800
1200
150
800
1200
150
800
1200
mV
tr,
tf
Rise/Fall Times @ 50 MHz
(20 - 80%)
110
180
250
125
190
275
150
215
300
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
26.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V.
27.Within-device skew is defined as identical transitions on similar paths through a device.
28.Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays
are measured from the cross point of the inputs to the cross point of the outputs.
0
100
200
300
400
500
600
700
800
900
0
1000
2000
3000
4000
5000
6000
Figure 4. Output Voltage Amplitude / RMS Jitter vs.
Input Frequency at Ambient Temperature (Typical)
INPUT FREQUENCY (MHz)
1
2
3
4
5
6
7
8
9


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