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MC100EP91DW 데이터시트(PDF) 3 Page - ON Semiconductor |
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3 / 10 page MC100EP91 http://onsemi.com 3 D1 D1 D2 17 18 16 15 14 13 12 4 3 56 78 9 Q0 11 10 Q1 Q1 Q2 Q2 NC VEE D0 19 20 2 1 VCC Q0 D0 D2 VCC VBB MC100EP91 GND GND VBB Figure 2. SOIC−20 Lead Pinout (Top View) VEE D2 GND Q0 D1 VCC VCC GND GND Q1 VBB NC VBB VCC GND Q1 D1 D2 Q2 VEE MC100EP91 Figure 3. QFN−24 Lead Pinout (Top View)* Q2 Q0 D0 D0 18 12 4 3 5 6 78 9 11 10 2 1 17 16 15 14 13 19 24 23 22 20 21 Exposed Pad (EP) *All VCC, VEE and GND pins must be externally connected to a power supply and the underside exposed pad must be attached to an adequate heat−sinking conduit to guarantee proper operation. Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor (R1) 75 kW Internal Input Pullup Resistor (R2) 75 kW ESD Protection Human Body Model Machine Model Charged Device Model > 2 kV > 150 V > 2 kV Moisture Sensitivity (Note 2) Pb Pkg Pb−Free Pkg SO−20 WB QFN−24 Level 1 Level 1 Level 3 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 446 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional information, see Application Note AND8003/D. |
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