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AD5930YRUZ-REEL7 데이터시트(PDF) 6 Page - Analog Devices

부품명 AD5930YRUZ-REEL7
상세설명  Programmable Frequency Sweep and Output Burst Waveform Generator
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

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AD5930
Rev. 0 | Page 6 of 28
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
See Figure 4 to Figure 7. DVDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, all specifications TMIN to TMAX, unless otherwise noted.
Table 2.1
Parameter
Limit at TMIN, TMAX
Unit
Conditions/Comments
t1
20
ns min
MCLK period
t2
8
ns min
MCLK high duration
t3
8
ns min
MCLK low duration
t4
25
ns min
SCLK period
t5
10
ns min
SCLK high time
t6
10
ns min
SCLK low time
t7
5
ns min
FSYNC to SCLK falling edge setup time
t8
10
ns min
FSYNC to SCLK hold time
t9
5
ns min
Data setup time
t10
3
ns min
Data hold time
t11
2 x t1
ns min
Minimum CTRL pulse width
t12
0
ns min
CTRL rising edge to MCLK falling edge setup time
t13
10 x t1
ns typ
CTRL rising edge to IOUT/IOUTB delay (initial pulse, includes initialization)
8 x t1
ns typ
CTRL rising edge to IOUT/IOUTB delay (initial pulse, includes initialization)
t14
2 x t1
ns typ
Frequency change to SYNC output, saw sweep, each frequency increment
t15
2 x t1
ns typ
Frequency change to SYNC output, saw sweep, end of sweep
t16
2 x t1
ns typ
Frequency change to SYNC output, triangle sweep, end of sweep
t17
20
ns max
MCLK falling edge after 16th clock edge to MSB out
1 Guaranteed by design, not production tested.
MCLK
t3
t2
t1
Figure 3. Master Clock
SCLK
FSYNC
SDATA
D15
D14
D2
D1
D0
D15
D14
t7
t9
t6
t8
t10
t5
t4
Figure 4. Serial Timing


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