AD8389

Rev. 0 | Page 5 of 12

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NC =

NO CONNECT

AD8389

TOP VIEW

(Not to Scale)

48-LEAD LFCSP

7mm

× 7mm

AVSS

1

MONITRI

2

MONITGI

3

MONITBI

4

AVDD

5

DXRO

ENBX1RO

ENBX2RO

ENBX3RO

ENBX4RO

36

35

34

33

32

AVSS

6

VCONTR

7

AVDD

8

AVSS

9

CLXRO

DXGO

ENBX1GO

ENBX2GO

ENBX3GO

31

30

29

28

27

ENBX4GO

26

CLXGO

25

PIN 1

INDICATOR

Figure 3. 48-Lead LFCSP, 7 mm × 7 mm Pin Configuration

Table 3. Pin Function Descriptions

Mnemonic

Function

Description

AVDD, DRVDD

Power Supply

Power Supply.

AVSS, DRVSS

Ground

Ground.

CLK

Clock

Clock Input. Active edge is the rising edge.

COMPEDGE

Edge Select

When set HIGH, the phase detector compares the falling edge of DXIN with the rising edge of

MONITxI. When set LOW, the phase detector compares the rising edge of DXIN with the falling

edge of MONITxI.

SLOW

Delay Select

When set HIGH and COMPEDGE = HIGH, the delay between the falling edges of DXI and the

COMPEDGE = LOW. When set LOW and COMPEDGE = HIGH, the delay between the falling edges

DXI

Reference Input

LCD Timing Input from the Image Processor. Used as the input to all phase detectors.

CLXI

Input

LCD Timing Input from the Image Processor.

ENBX(1–4)I

Inputs

LCD Timing Inputs from the Image Processor.

MONITxI

Feedback Inputs

Inputs from the LCD. Used as the feedback input to each phase detector. When the AD8389

forms part of a closed loop, it maintains a constant delay between the DXI input and this

reference input pin.

DXxO

Delayed Outputs

CLXxO

Delayed Outputs

ENBX(1–4)xO

Delayed Outputs

VCONTx

Control Voltage

200 pF capacitors connected between these pins and the AVSS plane are required for proper

operation of the internal charge pump.