전자부품 데이터시트 검색엔진 |
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AD9889BBSTZ-165 데이터시트(PDF) 8 Page - Analog Devices |
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AD9889BBSTZ-165 데이터시트(HTML) 8 Page - Analog Devices |
8 / 12 page AD9889B Preliminary Technical Data Rev. PrA | Page 8 of 12 Pin No. BGA LFCSP LQFP Mnemonic Type1 Description D5, D6, D7, E7 1, 48, 49 1, 61, 62, 63, 64 DVDD P 1.8 V Power Supply for Digital and I/O Power Supply. These pins supply power to the digital logic and I/Os. They should be filtered and as quiet as possible. G4, G5, J1 15, 16, 17, 16, 19, 20, 21 PVDD P 1.8 V PLL Power Supply. The most sensitive portion of the AD9889B is the clock generation circuitry. These pins provide power to the clock PLL. The designer should provide quiet, noise-free power to these pins. D4, E4, F4, J4, G6, J6, K6, F7, G7, H9, J9 64, paddle on bottom side 15, 17, 18, 22, 26, 32, 39, 42, 43, 59, 60, 79, 80 GND P Ground. The ground return for all circuitry on-chip. It is recommended that the AD9889B be assembled on a single, solid ground plane with careful attention given to ground current paths. F9 36 47 SDA C3 Serial Port Data I/O. This pin serves as the serial port data I/O slave for register access. Supports CMOS logic levels from 1.8 V to 3.3 V. F10 35 46 SCL C3 Serial Port Data Clock. This pin serves as the serial port data clock slave for register access. Supports CMOS logic levels from 1.8 V to 3.3 V. E10 37 48 MDA C3 Serial Port Data I/O Master to HDCP Key EEPROM. Supports CMOS logic levels from 1.8 V to 3.3 V. E9 38 49 MCL C3 Serial Port Data Clock Master to HDCP Key EEPROM. Supports CMOS logic levels from 1.8 V to 3.3 V. G9 34 45 DDCSDA C3 Serial Port Data I/O to Receiver. This pin serves as the master to the DDC bus. 5 V CMOS logic level. G10 33 44 DDCSCL C3 Serial Port Data Clock to Receiver. This pin serves as the master clock for the DDC bus. 5 V CMOS logic level. 1 I = input, O = output, P = power supply, C = control. 2 Pin J7 (BGA), Pin 26 (LFCSP), and Pin 33 (LQFP) are dual function pins: I2C selection and power-down control. The I2C selection function occurs at power-up; the power- down control function occurs whenever the state of the pin is changed from its original state at power-up. 3 For a full description of the 2-wire serial interface and its functionality obtain documentation by contacting NDA from flatpanel_apps@analog.com. |
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