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TSC2005I 데이터시트(PDF) 6 Page - Burr-Brown (TI) |
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TSC2005I 데이터시트(HTML) 6 Page - Burr-Brown (TI) |
6 / 42 page www.ti.com TIMING INFORMATION BIT0 t DIS(CSR-SDOZ) t H(SDI-SCLKR) NOTE: CPOL=0,CPHA=0,Byte0cyclerequires24SCLKs,andByte1cyclerequires8SCLKs. t H(SCLKF-SDOVALID) t SU(SDI-SCLKR) t D(CSF-SDOVALID) t SU(SCLKF-CSR) t WH(CS) t C(SCLK) t SU(CSF-SCLK1R) t F t R t WL(SCLK) t WH(SCLK) BIT1 MSBIN MSBOUT CS SS ( ) SCLK SDO(MISO) SDI(MOSI) BIT0 BIT1 TIMING REQUIREMENTS (1) TSC2005 SBAS379 – DECEMBER 2006 The TSC2005 supports SPI programming in mode CPOL = 0 and CPHA = 0. The falling edge of SCLK is used to change output (MISO) data and the rising edge is used to latch input (MOSI) data. Eight SCLKs are required to complete the Byte 1 command cycle, and 24 SCLKs are required for the Byte 0 command cycle. CS can stay low during the entire 24 SCLKs of a Byte 0 command cycle, or multiple mixed cycles of reading and writing of bytes and register accesses, as long as the corresponding addresses are supplied. Figure 1. Detailed I/O Timing All specifications typical at –40°C to +85°C, SNSVDD = I/OVDD = 1.6V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN MAX UNIT tWL(RESET) Reset low time I/OVDD = SNSVDD ≥ 1.6V(2) 10 µs I/OVDD ≥ 1.6V and < 2.7V, 40% to 60% duty cycle 60 ns tC(SCLK) SPI serial clock cycle time I/OVDD ≥ 2.7V and ≤ 3.6V, 40% to 60% duty cycle 40 ns I/OVDD ≥ 1.6V and < 2.7V, 10pF load 10 MHz fSCLK SPI serial clock frequency I/OVDD ≥ 2.7V and ≤ 3.6V, 10pF load 25 MHz tWH(SCLK) SPI serial clock high time 0.4 × tC(SCLK) 0.6 × tC(SCLK) ns tWL(SCLK) SPI serial clock low time 0.4 × tC(SCLK) 0.6 × tC(SCLK) ns tSU(CSF-SCLK1R) Enable lead time 30 ns tD(CSF-SDOVALID) Slave access time 15 ns tH(SCLKF-SDOVALID) MOSI data hold time 6 ns tD(SCLKF-SDOVALID) MISO data valid 13 ns tWH(CS) Sequential transfer delay 15 ns tSU(SDI-SCLKR) MOSI data setup time 6 ns tH(SDI-SCLKR) MISO data hold time 4 ns tDIS(CSR-SDOZ) Slave MISO disable time 15 ns tSU(SCLKF-CSR) Enable lag time 30 ns tR Rise time SNSVDD = I/OVDD = 3V, fSCLK = 25MHz 4 ns tF Fall time SNSVDD = I/OVDD = 3V, fSCLK = 25MHz 4 ns (1) All input signals are specified with tR = tF = 5ns (10% to 90% of I/OVDD) and timed from a voltage level of (VIL + VIH)/2. (2) Refer to Figure 30. 6 Submit Documentation Feedback |
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