OFST=1. Figure 3 illustrates the 2.048 MHz os-

cillator and dual D flip flop clock divider. Note

that both the oscillator and the divider are sepa-

rately decoupled from the +5V supply to reduce

clock jitter which can be introduced from noisy

supplies. Jumper J4 should be set in the CLK/2

position to source 1.024 MHz to the CS5322

chip for normal operation. If operation from

512 kHz clock is desired, the J4 jumper should

be changed to the CLK/4 position.

The board

can be tested at 512 kHz without modification.

The digital interface pins to the CS5322 filter

chip are all available on the header connectors

J1, J2, and J3 as shown in Figures 4, 5, and 6.

Note that one row of pins on each of the headers

is ground.

It is advised that any connections

made to control lines be done with twisted pair

ribbon cable; with each twisted pair containing

one signal and one ground connection.

This

minimizes radiated noise.

CAUTION!

Caution is advised when interfacing the evalu-

ation board to any circuitry powered from

another source. For example, when interfacing

to a computer I/O card be sure that the evalu-

ation board and the computer are both powered

up before connecting to the evaluation board

headers. Always disconnect header connections

when powering down the board but not the com-

puter. Failure to follow this advice may cause

damage to either the computer I/O or to the

CS5322, because the computer outputs try to

power the CDB5321 board.

Q

CLK

Q

0.1

10

OSC

14 pin

10

+ 10µF

7

74HC74

8

+5V

+5V

R3

C1

C2

R25

C33

2.048 MHz

14

U7

2

3

14

1

S

D

R

4

5

6

Q

CLK

Q

S

D

R

CLK/4 (512 kHz)

CLK/2 (1.024 MHz)

CLK (2.048 MHz)*

CLKIN (To Figure 4)

J4

10

9

8

13

11

12

U5A

U5B

*2.048 MHz

exceeds the

specified clock

frequency for

the CS5321

0.1

µF

Figure 3. Oscillator / Divider

CDB5321

18

DS88DB2