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ISL12029IV27AZ-T 데이터시트(PDF) 11 Page - Intersil Corporation |
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ISL12029IV27AZ-T 데이터시트(HTML) 11 Page - Intersil Corporation |
11 / 28 page 11 FN6206.6 October 18, 2006 read by performing a sequential read. The read instruction latches all Clock registers into a buffer, so an update of the clock does not change the time being read. A sequential read of the CCR will not result in the output of data from the memory array. At the end of a read, the master supplies a stop condition to end the operation and free the bus. After a read of the CCR, the address remains at the previous address +1 so the user can execute a current address read of the CCR and continue reading the next Register. Real Time Clock Registers (Volatile) SC, MN, HR, DT, MO, YR: Clock/Calendar Registers These registers depict BCD representations of the time. As such, SC (Seconds) and MN (Minutes) range from 00 to 59, HR (Hour) is 1 to 12 with an AM or PM indicator (H21 bit) or 0 to 23 (with MIL = 1), DT (Date) is 1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99. DW: Day of the Week Register This register provides a Day of the Week status and uses three bits DY2 to DY0 to represent the seven days of the week. The counter advances in the cycle 0-1-2-3-4-5-6-0-1- 2-… The assignment of a numerical value to a specific day of the week is arbitrary and may be decided by the system software designer. The default value is defined as ‘0’. Y2K: Year 2000 Register Can have value 19 or 20. As of the date of the introduction of this device, there would be no real use for the value 19 in a true real time clock, however. 24 Hour Time If the MIL bit of the HR register is 1, the RTC uses a 24-hour format. If the MIL bit is 0, the RTC uses a 12-hour format and H21 bit functions as an AM/PM indicator with a ‘1’, representing PM. The clock defaults to standard time with H21 = 0. Leap Years Leap years add the day February 29 and are defined as those years that are divisible by 4. Status Register (SR) (Volatile) The Status Register is located in the CCR memory map at address 003Fh. This is a volatile register only and is used to control the WEL and RWEL write enable latches, read power status and two alarm bits. This register is separate from both the array and the Clock/Control Registers (CCR). BAT: Battery Supply This bit set to “1” indicates that the device is operating from VBAT, not VDD. It is a read-only bit and is set/reset by hardware (ISL12029 internally). Once the device begins operating from VDD, the device sets this bit to “0”. AL1, AL0: Alarm Bits These bits announce if either alarm 0 or alarm 1 match the real time clock. If there is a match, the respective bit is set to ‘1’. The falling edge of the last data bit in a SR Read operation resets the flags. Note: Only the AL bits that are set when an SR read starts will be reset. An alarm bit that is set by an alarm occurring during an SR read operation will remain set after the read operation is complete. OSCF: Oscillator Fail Indicator This bit is set to “1” if the oscillator is not operating. The bit is set to “0” only if the oscillator is functioning. This bit is read only, and is set /reset by hardware. RWEL: Register Write Enable Latch This bit is a volatile latch that powers up in the LOW (disabled) state. The RWEL bit must be set to “1” prior to any writes to the Clock/Control Registers. Writes to RWEL bit do not cause a nonvolatile write cycle, so the device is ready for the next operation immediately after the stop condition. A write to the CCR requires both the RWEL and WEL bits to be set in a specific sequence. WEL: Write Enable Latch The WEL bit controls the access to the CCR during a write operation. This bit is a volatile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes to the CCR address will be ignored, although acknowledgment is still issued. The WEL bit is set by writing a “1” to the WEL bit and zeroes to the other bits of the Status Register. Once set, WEL remains set until either reset to 0 (by writing a “0” to the WEL bit and zeroes to the other bits of the Status Register) or until the part powers up again. Writes to WEL bit do not cause a nonvolatile write cycle, so the device is ready for the next operation immediately after the stop condition. RTCF: Real Time Clock Fail Bit This bit is set to a “1” after a total power failure. This is a read only bit that is set by hardware (ISL12029 internally) when the device powers up after having lost all power to the device (both VDD and VBAT go to 0V). The bit is set regardless of whether VDD or VBAT is applied first. The loss of only one of the supplies does not set the RTCF bit to “1”. On power up after a total power failure, all registers are set to their default states and the clock will not increment until at least one byte is written to the clock register. The first valid write to the RTC section after a complete power failure resets the RTCF bit to “0” (writing one byte is sufficient). Unused Bits: Bit 3 in the SR is not used, but must be zero. The Data Byte output during a SR read will contain a zero in this bit location. TABLE 1. STATUS REGISTER (SR) ADDR 7 6 5 4 3 2 1 0 003Fh BAT AL1 AL0 OSCF 0 RWEL WEL RTCF Default 0 0 0 0 0 0 0 1 ISL12029 |
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