5

SL1461SA

Advance Information

DESIGN OF PLL LOOP PARAMETERS

Fig.4

VCO

R2

C1

BASEBAND OUTPUT

R1

RF INPUT

The SL1461SA is normally used as a type 1 second order

loop and can be represented by the above diagram. For such

a system the following parameters apply;

1

2

1

K

2

n

2

2

n

and

where:

is the loop damping factor

R1 is loop amplifier input impedance

Note:

From these factors the loop 3dB bandwidth can be determined

from the following expression;

AFC FACILITY

The SL1461SA contains an analog frequency error

detect circuit, which generates DC voltage proportional to the

integral of frequency error. If the incident RF is high then the

AFC voltage increases, if low then the voltage decreases. The

AFC voltage can then be converted by an ADC to be read by

system it is recommended the device is used with either the

SP5055 or SP5056 frequency synthesiser which contains an

The voltage corresponding to frequency alignment is

arbitrary and user defined; if used with the SP5055 it is

the centre code of the ADC on port 6.

The AFC detect circuit contains a deadband centre

around the aligned frequency. The deadband can be adjusted

from zero window to approximately 25MHz width assuming an

oscillator dF/dV of 15MHz/V. If the incident RF is within this

window the AFC voltage does not integrate, except by

component leakage.

With reference to Fig.5; in normal operation the

demodulated video is fed to a dual comparator where it is

compared with two reference voltages, corresponding to the

extremes of the deadband, or window. These voltages are

variable and set by the window adjust input.

The comparators produce two digital outputs

corresponding to voltages above or below the voltage

window, or frequency above or below deadband. These digital

control signals are used to control a complimentary current

source pump. The current signals are then fed to the input of

an amplifier which is arranged as an integrator, so integrating

the

pulses into a DC voltage.

If the frequency is correctly aligned both the current

source and sink are disabled, therefore the DC output voltage

remains constant. There will be a small drift due to component

leakage; the maximum drift can be calculated from;