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Revision 1.0
5/18
28/April/2000
MTV130
MYSON
TECHNOLOGY
3.2 Address bus administrator
The administrator manages bus address arbitration of internal registers or user fonts RAM during external
data write in. The external data write through serial data interface to registers must be synchronized by inter-
nal display timing. In addition, the administrator also provides automatic increment to address bus when exter-
nal write using format (c).
3.3 Vertical display control
The vertical display control can generates different vertical display sizes for most display standards in current
monitors. The vertical display size is calculated with the information of double character height bit(CHS), verti-
cal display height control register(CH6-CH0).The algorithm of repeating character line display are shown as
Table 2 and Table 3. The programmable vertical size range is 270 lines to maximum 2130 lines.
The vertical display center for full screen display could be figured out according to the information of vertical
starting position register (VERTD) and VFLB input. The vertical delay starting from the leading edge of VFLB,
is calculated with the following equation:
Vertical delay time = ( VERTD * 4 + 1 ) * H
Where H = one horizontal line display time
TABLE 2. Repeat line weight of character
CH6 - CH0
Repeat Line Weight
CH6,CH5=11
+18*3
CH6,CH5=10
+18*2
CH6,CH5=0x
+18
CH4=1
+16
CH3=1
+8
CH2=1
+4
CH1=1
+2
CH0=1
+1
Initiate
ROW
COL
c
COL
ab
DA
c
DA
ab
1, X
0,
1
0,
0
X,
X
X,
X
0,
1
1, X
1, X
format (a)
format (b)
format (c)
X, X
0, X
Input = b7, b6
0, 0
FIGURE 3. Transmission State Diagram